Si4356
Rev 1.2 13
4. Functional Description
Figure 3. Si4356 Functional Block Diagram
The Si4356 is an easy-to-use, size efficient, low current wireless receiver that covers the sub-GHz bands. The wide
operating voltage range of 1.8–3.6 V and low current consumption make the Si4356 an ideal solution for battery
powered applications. The Si4356 uses a single-conversion mixer to downconvert the (G)FSK or OOK modulated
receive signal to a low IF frequency. Following a programmable gain amplifier (PGA), the signal is converted to the
digital domain by a high performance  ADC, thus allowing filtering and demodulation to be performed in the
built-in DSP and increasing the receiver's performance and flexibility versus analog based architectures. The
receiver demodulates the incoming data asynchronously by oversampling the incoming transmission. The resulting
demodulated signal is output to the system MCU through data output pin RX_DATA.
Integrated configuration tables allow the Si4356 to be completely configured using the four selector pins. The state
of each of these pins is read internally at startup and used to determine which pre-loaded configuration should be
used. The Si4356 then loads this configuration without the need for any external MCU control.
The Si4356 includes an integrated crystal oscillator. The design is differential with the typical crystal load
capacitance integrated on-chip to accommodate a 30 MHz off-chip crystal.
Rx Modem
Synthesizer
LNA
PGA
ADC
Rx Chain
Configuration Decoder
30MHz XO
RXp
RXn
VDD SEL0
CLK_OUT
RX_DATA / OUT1
XOUTXIN
SEL1 SEL3
STBY
SEL2
MSTAT / OUT0
÷
RST
GND
Si4356
14 Rev 1.2
5. Modes and Timing
At initial startup, the Si4356 reads the selector pins and loads all registers with the appropriate values for the
selected configuration, as shown in the Figure 4.
Figure 4. Power Up Timing
5.1. Power on Reset (POR)
A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To execute this
process, VDD must ramp within 1ms and must remain applied to the device for at least 10 ms. If VDD is removed,
then it must stay below 0.15 V for at least 10 ms before being applied again. See Figure 5 and Table 12 for details.
2 mA
3 mA
9mA
10 ms 8.5 ms
12 mA
3 ms
Total
Current
MSTAT
(Pin12)
RX_ DATA
(Pin14)
CLK_ OUT
(Pin10)
2.9 Vp-p
2.5 mA
1ms
V
DD
Si4356
Rev 1.2 15
Figure 5. POR Timing Diagram
The Si4356 provides two operating modes, a receive mode and a standby mode. The operating mode can be
changed by toggling STBY (pin 13) as described in Figure 6. Care should be taken to minimize the trace connected
to STBY to avoid external noise coupling that could result in unintended mode changes. The MSTAT signal (pin 12)
indicates the current operating mode of the device as defined in Table 13 and illustrated in Figure 6.
Table 12. POR Timing
Variable Description Min Typ Max Units
t
PORH
High time for VDD to fully settle POR circuit
10 ms
t
PORL
Low time for VDD to enable POR
10 ms
V
RRH
Voltage for successful POR
90% x Vdd V
V
RRL
Starting Voltage for successful POR
0150mV
t
SR
Slew rate of VDD for successful POR
1ms
Table 13. Operating Mode Status
Pin 12 (MSTAT) Mode
LOW Receive
HIGH Standby
V
DD
Time
V
RRH
t
SR
t
PORH
V
RRL

SI4356-B1A-FMR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
RF Receiver RX sub-GHz receiver
Lifecycle:
New from this manufacturer.
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