OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

CYRF6936-40LTXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
CYRF6936
Document Number: 38-16015 Rev. *K Page 4 of 30
Functional Overview
The CYRF6936 IC provides a complete WirelessUSB SPI to
antenna wireless MODEMs. The SoC is designed to implement
wireless device links operating in the worldwide 2.4 GHz ISM
frequency band. It is intended for systems compliant with
worldwide regulations covered by ETSI EN 301 489-1 V1.41,
ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA
and Industry Canada), and TELEC ARIB_T66_March, 2003
(Japan).
The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver,
packet data buffering, packet framer, DSSS baseband controller,
Received Signal Strength Indication (RSSI), and SPI interface
for data transfer and device configuration.
The radio supports 98 discrete 1 MHz channels (regulations may
limit the use of some of these channels in certain jurisdictions).
The baseband performs DSSS spreading/despreading, Start of
Packet (SOP), End of Packet (EOP) detection, and CRC16
generation and checking. The baseband may also be configured
to automatically transmit Acknowledge (ACK) handshake
packets whenever a valid packet is received.
When in receive mode, with packet framing enabled, the device
is always ready to receive data transmitted at any of the
supported bit rates. This enables the implementation of
mixed-rate systems in which different devices use different data
rates. This also enables the implementation of dynamic data rate
systems that use high data rates at shorter distances or in a
low-moderate interference environment or both. It changes to
lower data rates at longer distances or in high interference
environments or both.
In addition, the CYRF6936 IC has a Power Management Unit
(PMU), which enables direct connection of the device to any
battery voltage in the range 1.8 V to 3.6 V. The PMU conditions
the battery voltage to provide the supply voltages required by the
device, and may supply external devices.
Data Transmission Modes
The SoC supports four different data transmission modes:
■ In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
■ In 8DR mode, eight bits are encoded in each derived code
symbol transmitted.
■ In DDR mode, two bits are encoded in each derived code
symbol transmitted (As in the CYWUSB6934 DDR mode).
■ In SDR mode, one bit is encoded in each derived code symbol
transmitted (As in the CYWUSB6934 standard modes).
Both 64 chip and 32 chip Pseudo Noise (PN) codes are
supported. The four data transmission modes apply to the data
after the SOP. In particular the length, data, and CRC16 are all
sent in the same mode. In general, lower data rates reduce
packet error rate in any given environment.
Link Layer Modes
The CYRF6936 IC device supports the following data packet
framing features:
SOP
Packets begin with a two-symbol SoP marker. This is required in
GFSK and 8DR modes, but is optional in DDR mode and is not
supported in SDR mode. If framing is disabled then an SOP
event is inferred whenever two successive correlations are
detected. The SOP_CODE_ADR code used for the SOP is
different from that used for the “body” of the packet, and if desired
may be a different length. SOP must be configured to be the
same length on both sides of the link.
Length
There are two options for detecting the end of a packet. If SOP
is enabled, then the length field must be enabled. GFSK and
8DR must enable the length field. This is the first eight bits after
29 XOUT I/O O Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL
, or GPIO.
Tri-states in sleep mode (configure as GPIO drive LOW).
30 PACTL I/O O Control signal for external PA, T/R switch, or GPIO.
33 V
I/O
Pwr I/O interface voltage, 1.8–3.6 V.
34 RST I I Device reset. Internal 10 kohm pull down resistor. Active HIGH, connect
through a 0.47 F capacitor to V
BAT.
Must have RST = 1 event the first time
power is applied to the radio. Otherwise the state of the radio control registers
is unknown.
35 V
DD
Pwr Decoupling pin for 1.8 V logic regulator, connect through a 0.47 F capacitor
to GND.
37 L/D O PMU inductor/diode connection, when used. If not used, connect to GND.
40 V
REG
Pwr PMU boosted output voltage feedback.
E-PAD GND GND Must be soldered to Ground.
Corner Tabs NC NC Do Not solder the tabs and keep other signal traces clear. All tabs are common
to the lead frame or paddle which is grounded after the pad is grounded. While
they are visible to the user, they do not extend to the bottom.
Pin Definitions (continued)
Pin Number Name Type Default Description
CYRF6936
Document Number: 38-16015 Rev. *K Page 5 of 30
the SOP symbol, and is transmitted at the payload data rate.
When the length field is enabled, an EoP condition is inferred
after reception of the number of bytes defined in the length field,
plus two bytes for the CRC16. The alternative to using the length
field is to infer an EOP condition from a configurable number of
successive noncorrelations; this option is not available in GFSK
mode and is only recommended when using SDR mode.
CRC16
The device may be configured to append a 16 bit CRC16 to each
packet. The CRC16 uses the USB CRC polynomial with the
added programmability of the seed. If enabled, the receiver
verifies the calculated CRC16 for the payload data against the
received value in the CRC16 field. The seed value for the CRC16
calculation is configurable, and the CRC16 transmitted may be
calculated using either the loaded seed value or a zero seed; the
received data CRC16 is checked against both the configured
and zero CRC16 seeds.
CRC16 detects the following errors:
■ Any one bit in error.
■ Any two bits in error (irrespective of how far apart, which
column, and so on).
■ Any odd number of bits in error (irrespective of the location).
■ An error burst as wide as the checksum itself.
Figure 2 shows an example packet with SOP, CRC16, and
lengths fields enabled, and Figure 3 shows a standard ACK
packet.
Figure 2. Example Packet Format
Figure 3. Example ACK Packet Format
Packet Buffers
All data transmission and reception use the 16 byte packet
buffers - one for transmission and one for reception.
The transmit buffer allows loading a complete packet of up to 16
bytes of payload data in one burst SPI transaction. This is then
transmitted with no further MCU intervention. Similarly, the
receive buffer allows receiving an entire packet of payload data
up to 16 bytes with no firmware intervention required until the
packet reception is complete.
The CYRF6936 IC supports packets up to 255 bytes. However,
the actual maximum packet length depends on the accuracy of
the clock on each end of the link and the data mode. Interrupts
are provided to allow an MCU to use the transmit and receive
buffers as FIFOs. When transmitting a packet longer than 16
bytes, the MCU can load 16 bytes initially, and add further bytes
to the transmit buffer as transmission of data creates space in
the buffer. Similarly, when receiving packets longer than 16
bytes, the MCU must fetch received data from the FIFO
periodically during packet reception to prevent it from
overflowing.
P SOP 1 SOP 2 Length CRC 16
Payload Data
Preamble
n x 16us
1st Framing
Symbol*
2nd Framing
Symbol*
Packet
length
1 Byte
Period
*Note:32 or 64us
P SOP 1 SOP 2 CRC 16
Preamble
n x 16us
1st Framing
Symbol*
2nd Framing
Symbol*
CRC field from
received packet.
2 Byte periods
*Note:32 or 64us
CYRF6936
Document Number: 38-16015 Rev. *K Page 6 of 30
Auto Transaction Sequencer (ATS)
The CYRF6936 IC provides automated support for transmission
and reception of acknowledged data packets.
When transmitting in transaction mode, the device automatically:
■ starts the crystal and synthesizer
■ enters transmit mode
■ transmits the packet in the transmit buffer
■ transitions to receive mode and waits for an ACK packet
■ transitions to the transaction end state when an ACK packet is
received or a timeout period expires
Similarly, when receiving in transaction mode, the device
automatically:
■ waits in receive mode for a valid packet to be received
■ transitions to transmit mode, transmits an ACK packet
■ transitions to the transaction end state (receive mode to await
the next packet, and so on.)
The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without
any need for MCU firmware action (as long as packets of 16
bytes or less are used). To transmit data, the MCU must load the
data packet to be transmitted, set the length, and set the TX GO
bit. Similarly, when receiving packets in transaction mode,
firmware must retrieve the fully received packet in response to
an interrupt request indicating reception of a packet.
Data Rates
The CYRF6936 IC supports the following data rates by
combining the PN code lengths and data transmission modes
described in the previous sections:
■ 1000 kbps (GFSK)
■ 250 kbps (32 chip 8DR)
■ 125 kbps (64 chip 8DR)
■ 62.5 kbps (32 chip DDR)
■ 31.25 kbps (64 chip DDR)
■ 15.625 kbps (64 chip SDR)
Functional Block Overview
2.4 GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power, range, and robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in seven steps. The supply current of the
device is reduced as the RF output power is reduced.
Frequency Synthesizer
Before transmission or reception may begin, the frequency
synthesizer must settle. The settling time varies depending on
channel; 25 fast channels are provided with a maximum settling
time of 100 s.
The ‘fast channels’ (less than 100 s settling time) are every third
channel, starting at 0 up to and including 72 (for example, 0, 3,
6, 9 …. 69, 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception, CRC16
generation and checking, and EOP detection and length field.
Packet Buffers and Radio Configuration Registers
Packet data and configuration registers are accessed through
the SPI interface. All configuration registers are directly
addressed through the address field in the SPI packet (as in the
CYWUSB6934). Configuration registers allow configuration of
DSSS PN codes, data rate, operating mode, interrupt masks,
interrupt status, and so on.
SPI Interface
The CYRF6936 IC has an SPI interface supporting
communication between an application MCU and one or more
slave devices (including the CYRF6936). The SPI interface
supports single-byte and multi-byte serial transfers using either
4-pin or 3-pin interfacing. The SPI communications interface
consists of Slave Select (SS
), Serial Clock (SCK), Master
Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data
(SDAT).
SPI communication may be described as the following:
■ Command Direction (bit 7) = ‘1’ enables SPI write transaction.
A ‘0’ enables SPI read transactions.
■ Command Increment (bit 6) = ‘1’ enables SPI auto address
increment. When set, the address field automatically
increments at the end of each data byte in a burst access.
Otherwise the same address is accessed.
■ Six bits of address
■ Eight bits of data
Table 1. Internal PA Output Power Step Table
PA Setting Typical Output Power (dBm)
7+4
60
5–5
4 –13
3 –18
2 –24
1 –30
0 –35
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

CYRF6936-40LTXC

Mfr. #:
Buy CYRF6936-40LTXC
Manufacturer:
Cypress Semiconductor
Description:
RF Transceiver Wireless USB
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet