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CYRF6936-40LTXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
CYRF6936
Document Number: 38-16015 Rev. *K Page 7 of 30
The device receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI pin.
Data to the application MCU is shifted out on the MISO pin. The
active LOW Slave Select (SS) pin must be asserted to initiate an
SPI transfer.
The application MCU can initiate SPI data transfers using a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes shown in Table 2
through Figure 6 on page 8.
The SPI communications interface has a burst mechanism,
where the first byte can be followed by as many data bytes as
required. A burst transaction is terminated by deasserting the
slave select (SS
= 1).
The SPI communications interface single read and burst read
sequences are shown in Figure 4 on page 7 and Figure 5 on
page 7, respectively.
The SPI communications interface single write and burst write
sequences are shown in Figure 6 on page 8 and Figure 7 on
page 8, respectively.
This interface may be optionally operated in a 3-pin mode with
the MISO and MOSI functions combined in a single bidirectional
data pin (SDAT). When using 3-pin mode, user firmware must
ensure that the MOSI pin on the MCU is in a high impedance
state except when MOSI is actively transmitting data.
The device registers may be written to or read from one byte at
a time, or several sequential register locations may be written or
read in a single SPI transaction using incrementing burst mode.
In addition to single byte configuration registers, the device
includes register files. Register files are FIFOs written to and
read from using nonincrementing burst SPI transactions.
The IRQ pin function may be optionally multiplexed onto the
MOSI pin. When this option is enabled, the IRQ function is not
available while the SS
pin is LOW. When using this configuration,
user firmware must ensure that the MOSI pin on the MCU is in a
high impedance state whenever the SS pin is HIGH.
The SPI interface is not dependent on the internal 12 MHz clock.
Registers may therefore be read from or written to when the
device is in sleep mode, and the 12 MHz oscillator disabled.
The SPI interface and the IRQ and RST pins have a separate
voltage reference pin (V
I/O
). This enables the device to interface
directly to MCUs operating at voltages below the CYRF6936 IC
supply voltage.
Figure 4. SPI Single Read Sequence
Figure 5. SPI Incrementing Burst Read Sequence
Table 2. SPI Transaction Format
Parameter Byte 1 Byte 1+N
Bit # 7 6 [5:0] [7:0]
Bit Name DIR INC Address Data
CYRF6936
Document Number: 38-16015 Rev. *K Page 8 of 30
Figure 6. SPI Single Write Sequence
Figure 7. SPI Incrementing Burst Write Sequence
Interrupts
The device provides an interrupt (IRQ) output, which is configu-
rable to indicate the occurrence of various different events. The
IRQ pin may be programmed to be either active HIGH or active
LOW, and be either a CMOS or open drain output. The available
interrupts are described in the section Registers on page 15.
The CYRF6936 IC features three sets of interrupts: transmit,
receive, and system interrupts. These interrupts all share a
single pin (IRQ), but can be independently enabled or disabled.
The contents of the enable registers are preserved when
switching between transmit and receive modes.
If more than one interrupt is enabled at any time, it is necessary
to read the relevant status register to determine which event
caused the IRQ pin to assert. Even when a given interrupt source
is disabled, the status of the condition that would otherwise
cause an interrupt can be determined by reading the appropriate
status register. It is therefore possible to use the devices without
the IRQ pin, by polling the status registers to wait for an event,
rather than using the IRQ pin.
Clocks
A 12 MHz crystal (30 ppm or better) is directly connected
between XTAL and GND without the need for external
capacitors. A digital clock out function is provided, with
selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This
output may be used to clock an external microcontroller (MCU)
or ASIC. This output is enabled by default, but may be disabled.
The requirements to directly connect the crystal to the XTAL pin
and GND are:
■ Nominal Frequency: 12 MHz
■ Operating Mode: Fundamental Mode
■ Resonance Mode: Parallel Resonant
■ Frequency Stability: ±30 ppm
■ Series Resistance: <60 ohms
■ Load Capacitance: 10 pF
■ Drive Level: 100 µW
Power Management
The operating voltage of the device is 1.8 V to 3.6 V DC, which
is applied to the V
BAT
pin. The device can be shut down to a fully
static sleep mode by writing to the FRC END = 1 and
END STATE = 000 bits in the XACT_CFG_ADR register over the
SPI interface. The device enters sleep mode within 35 µs after
the last SCK positive edge at the end of this SPI transaction.
Alternatively, the device may be configured to automatically
enter sleep mode after completing the packet transmission or
reception. When in sleep mode, the on-chip oscillator is stopped,
but the SPI interface remains functional. The device wakes from
sleep mode automatically when the device is commanded to
enter transmit or receive mode. When resuming from sleep
mode, there is a short delay while the oscillator restarts. The
device can be configured to assert the IRQ pin when the
oscillator has stabilized.
The output voltage (V
REG
) of the Power Management Unit
(PMU) is configurable to several minimum values between 2.4 V
and 2.7 V. V
REG
may be used to provide up to 15 mA (average
load) to external devices. It is possible to disable the PMU and
provide an externally regulated DC supply voltage to the device’s
main supply in the range 2.4 V to 3.6 V. The PMU also provides
a regulated 1.8 V supply to the logic.
The PMU is designed to provide high boost efficiency (74–85%
depending on input voltage, output voltage, and load) when
using a Schottky diode and power inductor, eliminating the need
for an external boost converter in many systems where other
components require a boosted voltage. However, reasonable
efficiencies (69–82% depending on input voltage, output voltage,
CYRF6936
Document Number: 38-16015 Rev. *K Page 9 of 30
and load) may be achieved when using low cost components
such as SOT23 diodes and 0805 inductors.
The current through the diode must stay within the linear
operating range of the diode. For some loads the SOT23 diode
is sufficient, but with higher loads it is not and an SS12 diode
must be used to stay within this linear range of operation. Along
with the diode, the inductor used must not saturate its core. In
higher loads, a lower resistance/higher saturation coil such as
the inductor from Sumida must be used.
The PMU also provides a configurable low battery detection
function, which may be read over the SPI interface. One of seven
thresholds between 1.8 V and 2.7 V may be selected. The
interrupt pin may be configured to assert when the voltage on the
V
BAT
pin falls below the configured threshold. LV IRQ is not a
latched event. Battery monitoring is disabled when the device is
in sleep mode.
Low Noise Amplifier and Received Signal Strength
Indication
The gain of the receiver can be controlled directly by clearing the
AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of
the RX_CFG_ADR register. Clearing the LNA bit reduces the
receiver gain approximately 20 dB, allowing accurate reception
of very strong received signals (for example, when operating a
receiver very close to the transmitter). Approximately 30 dB of
receiver attenuation can be added by setting the Attenuation
(ATT) bit. This limits data reception to devices at very short
ranges. Disabling AGC and enabling LNA is recommended,
unless receiving from a device using external PA.
When the device is in receive mode the RSSI_ADR register
returns the relative signal strength of the on-channel signal
power.
When receiving, the device automatically measures and stores
the relative strength of the signal being received as a five bit
value. An RSSI reading is taken automatically when the SoP is
detected. In addition, a new RSSI reading is taken every time the
previous reading is read from the RSSI_ADR register, allowing
the background RF energy level on any given channel to be
easily measured when RSSI is read while no signal is being
received. A new reading can occur as fast as once every 12 µs.
Receive Spurious Response
The transmitter may exhibit spurs around 50 MHz offset at levels
approximately 50dB to 60dB below the carrier power. Receivers
operating at the transmit spur frequency may receive the spur if
the spur level power is greater than the receive sensitivity level.
The workaround for this is to program an additional byte in the
packet header which contains the transmitter channel number.
After the packet is received, the channel number can be
checked. If the channel number does not match the receive
channel then the packet is rejected.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

CYRF6936-40LTXC

Mfr. #:
Buy CYRF6936-40LTXC
Manufacturer:
Cypress Semiconductor
Description:
RF Transceiver Wireless USB
Lifecycle:
New from this manufacturer.
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