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STMPE1600QTR

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Interrupt status GPIO register (ISGPIOR) STMPE1600
16/27 Doc ID 16938 Rev 3
7 Interrupt status GPIO register (ISGPIOR)
ISGPIOR Interrupt status GPIO mask register
Address: 0x0A, 0x0B
Type: RW
Reset: 0
Description: Interrupt status GPIO register (ISGPIOR)
The ISGPIOR register monitors the status of the interruption from a particular GPIO
pin interrupt source to the host. Regardless of the IEGPIOR bits are enabled or not,
the ISGPIOR bits are still updated. The ISG[15:0] bits are the interrupt status bits
corresponding to the GPIO[15:0] pins.
1514131211109876543 2 1 0
ISG15 ISG14 ISG13 ISG12 ISG11 ISG10 ISG9 ISG8 ISG7 ISG6 ISG5 ISG4 ISG3 ISG2 ISG1 ISG0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
[15:0] ISG[x]: Interrupt status GPIO (where x = 15 to 0)
Read:
Interrupt Status of the GPIO[x]. Reading the register will clear any bits that has been set to ‘1’
Write:
Writing to this register has no effects
STMPE1600 GPIO controller
Doc ID 16938 Rev 3 17/27
8 GPIO controller
A total of 16 GPIOs are available in the STMPE1600 port expander IC. The GPIO controller
contains the registers that allow the host system to configure each of the pins into either a
GPIO (input or output), or into one of the alternate functions. Unused GPIOs should be
configured as outputs to minimize the power consumption.
A group of registers are used to control the exact function of each of the 16 GPIOs. The
registers and their respective address are listed in the following table.
Note: Once the last register address 0x16-0x17 location is accessed, the locations of 0x18 to
0xFF are reserved. After 0xFF location, the pointer rolls over to the 0x00 register address
location.
All GPIO registers are named as GPxx, where:
xx represents the functional group.
The function of each bit is shown in the following table:
On power-up reset, all GPIOs are set as input.
Table 8. GPIO controller registers
Address Register name Description
Auto-increment
(during sequential
R/W)
0x10 GPMR
GPIO monitor pin state
register
Ye s
0x12 GPSR
GPIO set pin state
register
Ye s
0x14 GPDR
GPIO set pin direction
register
Ye s
0x16 GPPIR
GPIO polarity inversion
register
Ye s
1514131211109876543 2 1 0
IO-15 IO-14 IO-13 IO-12 IO-11 IO-10 IO-9 IO-8 IO-7 IO-6 IO-5 IO-4 IO-3 IO-2 IO-1 IO-0
Table 9. GPIO bit function
Register name Function
GPIO monitor pin state Reading this bit yields the current state of the bit. Writing has no effect.
GPIO set pin state
Writing ‘1’ to this bit causes the corresponding GPIO to go to ‘1’ state.
Writing ‘0’ to this bit causes the corresponding GPIO to go to ‘0’ state.
GPIO set pin direction
‘0’ sets the corresponding GPIO to input state, and ‘1’ sets it to output
state. All bits are ‘0’ on reset.
GPIO polarity inversion
Writing a ‘1’ enables polarity inversion on the Input Port.
Writing a ‘0’, the input port polarity is retained. The reset value is 0.
Polarity inversion register STMPE1600
18/27 Doc ID 16938 Rev 3
9 Polarity inversion register
PINV Polarity inversion register
Address: 0x16, 0x17
Type: RW
Reset: 0
Description: Polarity inversion register.
This register allows the user to invert the polarity of the input port register data. If a bit
in this register is set (written with ‘1’), the Input Port Data polarity is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input Port Data polarity is retained. This
is for Active HIGH or Active LOW operation register. The polarity of the read register
can be inverted with this register.
9.1 Power supply
The STMPE1600 operates with a single power supply VCC that ranges from 1.65V to 3.6V.
The GPIO remains valid until the V
CC
is removed. When the V
CC
is removed, the GPIO is
reset.
9.2 Reset
The STMPE1600 is equipped with an internal POR circuit that holds the device in reset
state, until the V
CC
supply input is valid. The internal POR is tied to the V
CC
supply pin.
In the duration when reset pin is asserted, all GPIO are reset and default to input states.
1514131211109876543 2 1 0
PINV
15
PINV
14
PINV
13
PINV
12
PINV
11
PINV
10
PINV9 PINV8 PINV7 PINV6 PINV5 PINV4 PINV3 PINV2 PINV1 PINV0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
[15:0] PINV[x]: Polarity inversion register (where x = 15 to 0)
Writing a ‘1’ to the PINV[x] bit will enable polarity inversion on the Input Port. Writing a ‘0’, the
input port polarity is retained. The reset value is 0.
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STMPE1600QTR

Mfr. #:
Buy STMPE1600QTR
Manufacturer:
STMicroelectronics
Description:
Interface - I/O Expanders 16-bit Xpander Logic Ultra-Low Power
Lifecycle:
New from this manufacturer.
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