STMPE1600 I
2
C block
Doc ID 16938 Rev 3 7/27
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and followed by the slave device address. Accompanying the slave device
address, there is a Read/Write bit (R/W
). The bit is set to 1 for Read and 0 for write
operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from
the bus by not responding to the transaction.
Figure 4. I
2
C timing
Table 3. Eight programmable slave addresses
A2 A1 A0
Slave device address
(7-bit or 10-bit
addressing)
0 0 0 42h
0 0 1 43h
0 1 0 44h
0 1 1 45h
1 0 1 46h
1 0 1 47h
1 1 0 48h
1 1 1 49h
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I
2
C block STMPE1600
8/27 Doc ID 16938 Rev 3
Table 4. I
2
C bus timing
Symbol Parameter Min Typ Max Uni
f
SCL
SCL clock frequency 0 400 kHz
t
LOW
Clock low period 1.3 µs
t
HIGH
Clock high period 600 ns
t
F
SDA and SCL fall time 300 ns
t
HD:STA
START condition hold time (after this
period the first clock is generated)
600 ns
t
SU:STA
START condition setup time (only relevant
for a repeated start period)
600 ns
t
SU:DAT
Data setup time 100 ns
t
HD:DAT
Data hold time 0 µs
t
SU:STO
STOP condition setup time 600 ns
t
BUF
Time the bus must be free before a new
transmission can start
1.3 µs
STMPE1600 I2C features
Doc ID 16938 Rev 3 9/27
3 I
2
C features
The features that are supported by the I
2
C interface are as below:
–I
2
C slave device
Operates from 1.65 V to 3.6 V
Compliant to Philips I
2
C specification version 2.1
Supports standard (up to 100Kbps) and fast (up to 400Kbps) modes
7-bit and 10-bit device addressing modes with up to 8 slave device addresses
General call
Start/Restart/Stop
Address up to 8 STMPE1600 devices via I
2
C
Start condition
A Start condition is identified by a falling edge of SDA while SCL is stable at high state. A
Start condition must precede any data/command transfer. The device continuously monitors
for a Start condition and will not respond to any transaction unless one is encountered.
Stop condition
A Stop condition is identified by a rising edge of SDA while SCL is stable at high state. A
Stop condition terminates communication between the slave device and bus master. A read
command that is followed by NoAck can be followed by a Stop condition to force the slave
device into idle mode. When the slave device is in idle mode, it is ready to receive the next
I2C transaction. A Stop condition at the end of a write command stops the write operation to
registers.
Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDA after sending eight bits of data. During the ninth bit, the receiver pulls the
SDA low to acknowledge the receipt of the eight bits of data. The receiver may leave the
SDA in high state if it would to not acknowledge the receipt of the data.
Data input
The device samples the data input on SDA on the rising edge of the SCL. The SDA signal
must be stable during the rising edge of SCL and the SDA signal must change only when
SCL is driven low.

STMPE1600QTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Interface - I/O Expanders 16-bit Xpander Logic Ultra-Low Power
Lifecycle:
New from this manufacturer.
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