LTC4274
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the OUT pin and measuring the resulting current; it then
reports the discovered class in the Port Status register. If
the LTC4274 is in AUTO pin mode, it will additionally use
the classification result to set the I
CUT
and I
LIM
thresholds.
See the Reset and the AUTO/MID Pin section for more
information.
The classification circuitry is disabled when the port is
initially powered up with the AUTO pin low, in shutdown
mode, or when the corresponding Class Enable bit is
cleared.
802.3at 2-Event Classification
The 802.3at spec defines two methods of classifying a
Type 2 PD.
One method adds extra fields to the Ethernet LLDP data
protocol; although the LTC4274 is compatible with this
classification method, it cannot perform classification
directly since it doesnt have access to the data path.
LLDP classification requires the PSE to power the PD as
a standard 802.3af (Type 1) device. It then waits for the
host to perform LLDP communication with the PD and
update the PSE port data. The LTC4274 supports chang-
ing the I
LIM
and I
CUT
levels on the fly, allowing the host
to complete LLDP classification.
The second 802.3at classification method, known as
2-event classification or ping-pong, is fully supported by
the LTC4274. A Type 2 PD that is requesting more than
13W will indicate Class 4 during normal 802.3af classifica-
tion. If the LTC4274 sees Class 4, it forces the port to a
specified lower voltage (called the mark voltage, typically
9V), pauses briefly, and then re-runs classification to
verify the Class 4 reading
(Figure 1). It also sets a bit in
the High Power Status register to indicate that it ran the
second classification cycle. The second cycle alerts the
PD that it is connected to a Type 2 PSE which can supply
Type 2 power levels.
2-event ping-pong classification is enabled by setting a
bit in the ports High Power Mode register. Note that a
ping-pong enabled port only runs the second classification
cycle when it detects a Class 4 device; if the first cycle
returns Class 0 to 3, the port assumes it is connected to a
Type1 PD and does not run the second classification cycle.
Invalid Type 2 Class Combinations
The 802.3at spec defines a Type 2 PD class signature as
two consecutive Class 4 results; a Class 4 followed by a
Class 0-3 is not a valid signature. In AUTO pin mode, the
LTC4274 will power a detected PD regardless of the clas-
sification results, with one exception: if the PD presents
an invalid Type 2 signature (Class 4 followed by Class 0
to 3), the LTC4274 will not provide power and will restart
the detection process. To aid in diagnosis, the Port Status
register will always report the results of the last class pulse,
so an invalid Class 4–Class 2 combination would report
a second class pulse was run in the High Power Status
register (which implies that the first cycle found Class 4),
and Class 2 in the Port Status register.
POWER CONTROL
External MOSFET, Sense R Summary
The primary function of the LTC4274 is to control the
delivery of power to the PSE port. It does this by control-
ling the gate drive voltage of an external power MOSFET
while monitoring the current via an external sense resis-
tor and the output voltage at the OUT pin. This circuitry
serves to couple the raw V
EE
input supply to the port in
a controlled manner that satisfies the PDs power needs
while minimizing power dissipation in the MOSFET and
disturbances on the V
EE
backplane.
The LTC4274 is designed to use 0.25Ω sense resistors to
minimize power dissipation. It also supports 0.5Ω sense
resistors, which are the default when LTC4258/LTC4259A
compatibility is desired.
Inrush Control
Once the command has been given to turn on the port,
the LTC4274 ramps up the GATE pin of the ports external
MOSFET in a controlled manner. Under normal power-up
circumstances, the MOSFET gate will rise until the port
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current reaches the inrush current limit level (typically
450mA), at which point the GATE pin will be servoed to
maintain the specified I
INRUSH
current. During this inrush
period, a timer (t
START
) runs. When output charging is
complete, the port current will fall and the GATE pin will
be allowed to continue rising to fully enhance the MOSFET
and minimize its on-resistance. The final V
GS
is nominally
12V. If the t
START
timer expires before the inrush period
completes, the port will be turned back off and a t
START
fault reported.
Current Limit
The LTC4274 port includes two current limiting thresholds
(I
CUT
and I
LIM
), each with a corresponding timer (t
CUT
and t
LIM
). Setting the I
CUT
and I
LIM
thresholds depends
on several factors: the class of the PD, the voltage of the
main supply (V
EE
), the type of PSE (1 or 2), the sense
resistor (0.5Ω or 0.25Ω), the SOA of the MOSFET, and
whether or not the system is required to implement class
enforcement.
Per the IEEE spec, the LTC4274 will allow the port cur-
rent to exceed I
CUT
for a limited period of time before
removing power from the port, whereas it will actively
control the MOSFET gate drive to keep the port current
below I
LIM
. The port does not take any action to limit the
current when only the I
CUT
threshold is exceeded, but
does start the t
CUT
timer. The t
LIM
timer starts when the
I
LIM
threshold is exceeded and current limit is active. If
the current drops below the I
CUT
current threshold before
its timer expires, the t
CUT
timer counts back down, but
at 1/16 the rate that it counts up. This allows the current
limit circuitry to tolerate intermittent overload signals with
duty cycles below about 6%; longer duty cycle overloads
will turn the port off.
I
CUT
is typically set to a lower value than I
LIM
to allow the
port to tolerate minor faults without current limiting.
Per the IEEE specification, the LTC4274 will automatically
set I
LIM
to 425mA (shown in bold in Table 5) during in-
rush at port turn-on, and then switch to the programmed
I
LIM
setting once inrush has completed. To maintain IEEE
compliance, I
LIM
should kept at 425mA for all Type 1 PDs,
and 850mA if a Type 2 PD is detected. I
LIM
is automatically
reset to 425mA when a port turns off.
Table 5. Example Current Limit Settings
I
LIM
(mA)
INTERNAL REGISTER SETTING (hex)
R
SENSE
= 0.5Ω R
SENSE
= 0.25Ω
53 88
106 08 88
159 89
213 80 08
266 8A
319 09 89
372 8B
425 00 80
478 8E
531 92 8A
584 CB
638 10 90
744 D2 9A
850 40 C0
956 4A CA
1063 50 D0
1169 5A DA
1275 60 E0
1488 52 49
1700 40
1913 4A
2125 50
2338 5A
2550 60
2975 52
I
LIM
Foldback
The LTC4274 features a two-stage foldback circuit that
reduces the port current if the port voltage falls below
the normal operating voltage. This keeps MOSFET power
dissipation at safe levels for typical 802.3af MOSFETs,
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even at extended 802.3at power levels. Current limit and
foldback behavior are programmable. Figure 14 shows
MOSFET power dissipation with 802.3af-style foldback
compared with a typical MOSFET SOA curve; Figure 15
demonstrates how two-stage foldback keeps the FET
within its SOA under the same conditions. Table 5 gives
examples of recommended I
LIM
register settings.
The LTC4274 will support current levels well beyond the
maximum values in the 802.3at specification. The shaded
areas in Table 5 indicate settings that may require a larger
external MOSFET, additional heat sinking, or a reduced
t
LIM
setting.
MOSFET Fault Detection
The LTC4274 PSE port is designed to tolerate significant
levels of abuse, but in extreme cases it is possible for the
external MOSFET to be damaged. A failed MOSFET may
short source to drain, which will make the port appear to
be on when it should be off; this condition may also cause
the sense resistor to fuse open, turning off the port but
causing the LTC4274 SENSE pin to rise to an abnormally
high voltage. A failed MOSFET may also short from gate
to drain, causing the LTC4274 GATE pin to rise to an ab-
normally high voltage. The LTC4274 SENSE and GATE pins
are designed to tolerate up to 80V faults without damage.
If the LTC4274 sees any of these conditions for more than
180μs, it disables all port functionality, reduces the gate
drive pull-down current for the port and reports a FET Bad
fault. This is typically a permanent fault, but the host can
attempt to recover by resetting the port, or by resetting
the entire chip if a port reset fails to clear the fault. If the
MOSFET is in fact bad, the fault will quickly return, and
the port will disable itself again.
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a t
START
fault if the LTC4274 attempts
to turn on the port.
Voltage and Current Readback
The LTC4274 measures the output voltage and current
at the port with an internal A/D converter. Port data is
only valid when the port power is on. The converter has
two modes:
Slow mode: 14 samples per second, 14.5 bits resolution
Fast mode: 440 samples per second, 9.5 bits resolution
In fast mode, the least significant 5 bits of the lower byte
are zeroes so that bit scaling is the same in both modes.
Disconnect
The LTC4274 monitors the port to make sure that the PD
continues to draw the minimum specified current. A dis-
connect timer counts up whenever port current is below
7.5mA (typ), indicating that the PD has been disconnected.
If the t
DIS
timer expires, the port will be turned off and
the disconnect bit in the fault event register will be set.
If the current returns before the t
DIS
timer runs out, the
Figure 14. Turn On Currents vs FET Safe Operating
Area at 90°C Ambient
Figure 15. LTC4274 Foldback vs FET Safe Operating
Area at 90°C Ambient
PD Voltage (V) at V
PSE
= 58V
0
0.0
PSE Current (A)
0.2
0.4
0.6
10
20
30 40
4274 F14
50
0.8
1.0
0.1
0.3
0.5
0.7
0.9
60
802.3af FOLDBACK
2 x 802.3af FOLDBACK
SOA 75ms AT 25°C
SOA DC AT 90°C
PD Voltage (V) at V
PSE
= 58V
0
0.0
PSE Current (A)
0.2
0.4
0.6
10
20
30 40
4274 F15
50
0.8
1.0
0.1
0.3
0.5
0.7
0.9
60
LTC4274 FOLDBACK
802.3af FOLDBACK
SOA DC AT 90°C
SOA 75ms AT 90°C
SOA 75ms AT 25°C

LTC4274IUHF#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN PoE+ 25.5W Single PSE Controller
Lifecycle:
New from this manufacturer.
Delivery:
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