LTC4274
25
4274fe
For more information www.linear.com/LTC4274
Sense Resistor
The LTC4274 is designed to use either 0.5Ω or 0.25Ω current
sense resistors. For new designs 0.25Ω is recommended to
reduce power dissipation; the 0.5Ω option is intended for
existing systems where the LTC4274 is used as a drop-in
replacement for the LTC4258 or LTC4259A. The lower sense
resistor values reduce heat dissipation. Four commonly avail-
able 1Ω resistors (0402 or larger package size) can be used
in parallel in place of a single 0.25Ω resistor. In order to meet
the I
CUT
and I
LIM
accuracy required by the IEEE specification,
the sense resistors should have ±1% tolerance or better, and
no more than ±200ppm/°C temperature coefficient.
Output Cap
The port requires a 0.22μF cap across its output to keep
the LTC4274 stable while in current limit during startup or
overload. Common ceramic capacitors often have significant
voltage coefficients; this means the capacitance is reduced as
the applied voltage increases. To minimize this problem, X7R
ceramic capacitors rated for at least 100V are recommended.
Surge Protection
Ethernet ports can be subject to significant cable surge
events. To keep PoE voltages below a safe level and protect
the application against damage, protection components, as
shown in Figure 19, are required at the main supply, at the
LTC4274 pins, and at each port.
Bulk transient voltage suppression (TVS
BULK
) and bulk ca-
pacitance (C
BULK
) are required across the main PoE supply
and should be sized to accommodate system level surge
requirements. A large capacitance of 10μF or greater
(C3)
is required across the +3.3V supply if V
DD
is above AGND.
Each LTC4274 requires a 10Ω, 0805 resistor (R1) in series
from supply AGND to the LTC4274 AGND pin. Across the
LTC4274 AGND pin and V
EE
pin are an SMAJ58A, 58V
TVS (D1) and a 1μF, 100V bypass capacitor (C1). These
components must be placed close to the LTC4274 pins.
If the V
DD
supply is above AGND, each LTC4274 requires
a 10Ω, 0805 resistor (R2) in series from the +3.3V supply
positive rail to the LTC4274 V
DD
pin. Across the LTC4274
V
DD
pin and DGND pin are an SMAJ5.0A, 5.0V TVS (D2)
and a 0.1μF capacitor (C2). These components must be
placed close to the LTC4274 pins. DGND is tied directly to
the protected AGND pin. Pull-ups at the logic pins should
be to the protected side of the 10Ω resistors at the V
DD
pin. Pull-downs at the logic pins should be to the protected
side of the 10Ω resistors at the tied AGND and DGND pins.
Finally,
each port requires a pair of S1B clamp diodes,
one from OUTn to supply AGND (D3) and one from OUTn
to supply V
EE
(D4). The diodes at the ports steer harmful
surges into the supply rails where they are absorbed by the
surge suppressors and the V
EE
bypass capacitance. The
layout of these paths must be low impedance.
Further considerations include LTC4274 applications with
off-board connections, such as a daughter card to a mother
board or headers to an external supply or host control board.
Additional protection may be required at the LTC4274 pins
to these off-board connections.
LAYOUT GUIDELINES
Standard power layout guidelines apply to the LTC4274:
place the decoupling caps for the V
DD
and V
EE
supplies
near their respective supply pins, use ground planes, and
use wide traces wherever there are significant currents.
APPLICATIONS INFORMATION
Figure 19. LTC4274 Surge Protection
D4 S1B
C
OUT
0.22μF
100V
X7R
1µF
100V
X7R
V
EE
SENSE GATE OUT
V
DD
AUTO
SCL
SDAIN
DGND
AGND
R
S
Q1
LTC4274
–54V
4274 F19
D3
S1B
OUTn
C2
0.1µF
D2
SMAJ5.0A
R2
10Ω
C3
10µF
C
BULK
TVS
BULK
+3.3V
D1
SMAJ58A
R1
10Ω
