6.4210
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range
Application Example
SRAM #1
A
LD
R/
W
BW
0
BW
1
C
C
K
K
DQ
ZQ
A
LD
BW
0
BW
1
C
C
K
K
DQ
ZQ
R=250
R=250
V
t
Data Bus
Address
LD
R/
W
MEMORY
CONTROLLER
Return CLK
Source CLK
Return
CLK
Source
CLK
R=50
V
t
R
Vt
=V
REF
V
t
V
t
R
6112 drw 20
SRAM #4
BWx
/
NWx
R/
W
SS
V
t
t
V
R
R
R
R
6.42
11
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range
Absolute Maximum Ratings
(1) (2)
Capacitance (TA = +25°C, f = 1.0MHz)
(1)
Symbol
Rating
Value
Unit
V
TERM
Supply Voltage on V
DD
with
Re spect to GND
–0.5 to +2.9 V
V
TERM
Supply Voltage on V
DDQ
with
Re spect to GND
–0.5 to V
DD
+0.3 V
V
TERM
Vo ltag e on Inp ut te rm inals with
re s pe c t to G ND
–0.5 to V
DD
+0.3 V
V
TERM
Voltage on Output and I/O
te rm inals with re s p e c t to G ND.
–0.5 to V
DDQ
+0.3 V
T
BIAS
Temperature Under Bias –55 to +125 °C
T
STG
Storage Temperature –65 to +150 °C
I
OUT
Continuous Current into Outputs + 20 mA
6112 tbl 05
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
DD
= 1.8V
V
DDQ
= 1.5V
5pF
C
CLK
Clock Input Capacitance 6 pF
C
O
Output Capacitance 7 pF
6112 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VDDQ must not exceed VDD during normal operation.
NOTE:
1. Tested at characterization and retested after any design or process change that
may affect these parameters.
Recommended DC Operating and
Temperature Conditions
Symbol
Parameter
Min.
Typ .
Max.
Unit
V
DD
Power Supply
Voltage
1.7 1.8 1.9 V
V
DDQ
I/O Supply Voltage 1.4 1.5 1.9 V
V
SS
Ground 0 0 0 V
V
REF
Input Reference
Voltage
0.68 V
DDQ
/2 0.95 V
T
A
Ambient
Temperature
(1)
0
_
+70
o
c
6112 tbl 04
NOTE:
1. During production testing, the case temperature equals the ambient
temperature.
6.4212
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range
(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Note
Input Leakage Current
I
IL
V
DD
= Max V
IN
= V
SS
to V
DDQ
-10
+10
µ
A
Output Leakage Current
I
OL
Output Disabled
-10
+10
µ
A
Operating Current
(x36,x18,x9,x8): DDR
I
DD
V
DD
= Max,
I
OUT
= 0mA (outputs open),
Cycle Time
>
t
KHKH
Min
333MH
Z
-
TBD
mA
1
300MH
Z
-
TBD
250MH
Z
-
TBD
200MHz
-
TBD
167MHz
-
TBD
Standby Current: NOP
I
SB1
Device Deselected (in NOP state),
I
OUT
= 0mA (outputs open),
f=Max,
All Inputs
<
0.2V or
>
VDD -0.2V
333MH
Z
-
TBD
mA
2
300MH
Z
-
TBD
250MH
Z
-
TBD
200MHz
-
TBD
167MHz
-
TBD
Output High Voltage
V
OH1
RQ = 250
Ω,
I
OH
= -15mA
V
DDQ
/2-0.12
V
DDQ
/2+0.12
V
3,7
Output Low Voltage
V
OL1
RQ = 250
Ω,
I
OH
= 15mA
V
DDQ
/2-0.12
V
DDQ
/2+0.12
V
4,7
Output High Voltage
V
OH2
I
OH
= -0.1mA
V
DDQ
-0.2
V
DDQ
V
5
Output Low Voltage
V
OL2
I
OL
= 0.1mA
V
SS
0.2
V
6
6112 tb l 10 c
NOTES:
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175 < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175 < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.

IDT71P71804S200BQG8

Mfr. #:
Manufacturer:
Description:
IC SRAM 18M PARALLEL 165CABGA
Lifecycle:
New from this manufacturer.
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