6.4214
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range
AC Electrical Characteristics (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, TA =0 to 70°C)
(3,8)
Symbol Parameter
333MHz 300MHz 250MHz 200MHz 167MHz
Unit Notes
Min. Max Min. Max Min. Max Min. Max Min. Max
Clock Parameters
t
KHKH
Average clock cycle time (K,K,C,C) 3.00 3.47 3.30 5.25 4.00 6.30 5.00 7.88 6.00 8.40 ns
t
KC var
Cycle to Cycle Period Jitter (K,K,C,C) - 0.20 - 0.20 - 0.20 - 0.20 - 0.20 ns 1,5
t
KHKL
Clock High Time (K,K,C,C) 1.20 - 1.32 - 1.60 - 2.00 - 2.40 - ns 9
t
KLKH
Clock LOW Time (K,K,C,C) 1.20 - 1.32 - 1.60 - 2.00 - 2.40 - ns 9
t
KH
K
H
Clock to clock (K→K,C→C) 1.35 - 1.49 - 1.80 - 2.20 - 2.70 - ns 10
t
K
HKH
Clock to clock (K→K,C→C)
1.35 - 1.49 - 1.80 - 2.20 - 2.70 - ns 10
t
KHCH
Clock to data clock (K→C,K→C) 0.00 1.30 0.00 1.45 0.00 1.80 0.00 2.30 0.00 2.80 ns
t
KC lock
DLL lock time (K, C) 1024 - 1024 - 1024 - 1024 - 1024 - cycles 2
t
KC reset
K static to DLL reset 30 - 30 - 30 - 30 - 30 - ns
Output Parameters
t
CHQV
C,C HIGH to output valid - 0.45 - 0.45 - 0.45 - 0.45 - 0.50 ns 3
t
CHQX
C,C HIGH to output hold -0.45 - -0.45 - -0.45 - -0.45 - -0.50 - ns 3
t
CHCQV
C,C HIGH to echo clock valid - 0.45 - 0.45 - 0.45 - 0.45 - 0.50 ns 3
t
CHCQX
C,C HIGH to echo clock hold -0.45 - -0.45 - -0.45 - -0.45 - -0.50 - ns 3
t
CQHQV
CQ,CQ HIGH to output valid - 0.25 - 0.27 - 0.30 - 0.35 - 0.40 ns
t
CQHQX
CQ,CQ HIGH to output hold -0.25 - -0.27 - -0.30 - -0.35 - -0.40 - ns
t
CHQZ
C HIGH to output High-Z - 0.45 - 0.45 - 0.45 - 0.45 - 0.50 ns 3,4,5
t
CHQX1
C HIGH to output Low-Z -0.45 - -0.45 - -0.45 - -0.45 - -0.50 - ns 3,4,5
Set-Up Times
t
AV K H
Address valid to K,K rising edge 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 6
t
IV KH
Control inputs valid to K,K rising edge 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 7
t
DVKH
Date-in valid to K, K rising edge 0.30 - 0.30 - 0.35 - 0.40 - 0.50 - ns
Hold Times
t
KHAX
K,K rising edge to address hold 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 6
t
KHIX
K,K rising edge to control inputs hold 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 7
t
KHDX
K, K rising edge to data-in hold 0.30 - 0.30 - 0.35 - 0.40 - 0.50 - ns
6112 tbl 11
NOTES:
1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No.65 (EIA/JESD65) pg.10
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. Control signals are R, W,BW0,BW1 and (NW0,NW1, for x8) and (BW2,BW3 also for x36)
8. During production testing, the case temperature equals TA.
9. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
10. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
