10
LTC3736
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Main Control Loop
The LTC3736 uses a constant frequency, current mode
architecture with the two controllers operating 180 de-
grees out of phase. During normal operation, the top
external P-channel power MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the current comparator (I
CMP
) resets the latch. The
peak inductor current at which I
CMP
resets the RS latch is
determined by the voltage on the I
TH
pin, which is driven
by the output of the error amplifier (EAMP). The V
FB
pin
receives the output voltage feedback signal from an exter-
nal resistor divider. This feedback signal is compared to
the internal 0.6V reference voltage by the EAMP. When the
load current increases, it causes a slight decrease in V
FB
relative to the 0.6V reference, which in turn causes the I
TH
voltage to increase until the average inductor current
matches the new load current. While the top P-channel
MOSFET is off, the bottom N-channel MOSFET is turned
on until either the inductor current starts to reverse, as
indicated by the current reversal comparator, I
RCMP
, or the
beginning of the next cycle.
Shutdown, Soft-Start and Tracking Start-Up
(RUN/SS and TRACK Pins)
The LTC3736 is shut down by pulling the RUN/SS pin low.
In shutdown, all controller functions are disabled and the
chip draws only 9µA. The TG outputs are held high (off)
and the BG outputs low (off) in shutdown. Releasing
RUN/SS allows an internal 0.7µA current source to charge
up the RUN/SS pin. When the RUN/SS pin reaches 0.65V,
the LTC3736’s two controllers are enabled.
The start-up of V
OUT1
is controlled by the LTC3736’s
internal soft-start. During soft-start, the error amplifier
EAMP compares the feedback signal V
FB1
to the internal
soft-start ramp (instead of the 0.6V reference), which rises
linearly from 0V to 0.6V in about 1ms. This allows the
output voltage to rise smoothly from 0V to its final value,
while maintaining control of the inductor current.
The 1ms soft-start time can be increased by connecting
the optional external soft-start capacitor C
SS
between the
RUN/SS and SGND pins. As the RUN/SS pin continues to
OPERATIO
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rise linearly from approximately 0.65V to 1.3V (being
charged by the internal 0.7µA current source), the EAMP
regulates the V
FB1
proportionally linearly from 0V to 0.6V.
The start-up of V
OUT2
is controlled by the voltage on the
TRACK pin. When the voltage on the TRACK pin is less
than the 0.6V internal reference, the LTC3736 regulates
the V
FB2
voltage to the TRACK pin instead of the 0.6V
reference. Typically, a resistor divider on V
OUT1
is con-
nected to the TRACK pin to allow the start-up of V
OUT2
to
“track” that of V
OUT1
. For one-to-one tracking during start-
up, the resistor divider would have the same values as the
divider on V
OUT2
that is connected to V
FB2
.
Light Load Operation (Burst Mode or Continuous
Conduction) (SYNC/FCB Pin)
The LTC3736 can be enabled to enter high efficiency Burst
Mode operation or forced continuous conduction mode at
low load currents. To select Burst Mode operation, tie the
SYNC/FCB pin to a DC voltage above 0.6V (e.g., V
IN
). To
select forced continuous operation, tie the SYNC/FCB to a
DC voltage below 0.6V (e.g., SGND). This 0.6V threshold
between Burst Mode operation and forced continuous mode
can be used in secondary winding regulation as described
in the Auxiliary Winding Control Using SYNC/FCB Pin dis-
cussion in the Applications Information section.
When a controller is in Burst Mode operation, the peak
current in the inductor is set to approximate one-fourth of
the maximum sense voltage even though the voltage on
the I
TH
pin indicates a lower value. If the average inductor
current is lower than the load current, the EAMP will
decrease the voltage on the I
TH
pin. When the I
TH
voltage
drops below 0.85V, the internal SLEEP signal goes high
and both external MOSFETs are turned off.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3736 draws.
The load current is supplied by the output capacitor. As
the output voltage decreases, the EAMP increases the I
TH
voltage. When the I
TH
voltage reaches 0.925V, the SLEEP
signal goes low and the controller resumes normal
operation by turning on the external P-channel MOSFET
on the next cycle of the internal oscillator.
(Refer to Functional Diagram)
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LTC3736
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When a controller is enabled for Burst Mode operation, the
inductor current is not allowed to reverse. Hence, the
controller operates discontinuously. The reverse current
comparator (RICMP) senses the drain-to-source voltage
of the bottom external N-channel MOSFET. This MOSFET
is turned off just before the inductor current reaches zero,
preventing it from reversing and going negative.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by the
voltage on the I
TH
pin. The P-channel MOSFET is turned on
every cycle (constant frequency) regardless of the I
TH
pin
voltage. In this mode, the efficiency at light loads is lower
than in Burst Mode operation. However, continuous mode
has the advantages of lower output ripple and less inter-
ference with audio circuitry.
When the SYNC/FCB pin is clocked by an external clock
source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop), the LTC3736 operates
in PWM pulse skipping mode at light loads. In this mode,
the current comparator I
CMP
may remain tripped for
several cycles and force the external P-channel MOSFET to
stay off for the same number of cycles. The inductor
current is not allowed to reverse, though (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. However, it provides low current efficiency
higher than forced continuous mode, but not nearly as
high as Burst Mode operation. During start-up or a short-
circuit condition (V
FB1
or V
FB2
0.54V), the LTC3736
operates in pulse skipping mode (no current reversal
allowed), regardless of the state of the SYNC/FCB pin.
Short-Circuit Protection
When an output is shorted to ground (V
FB
< 0.12V), the
switching frequency of that controller is reduced to 1/5 of
the normal operating frequency. The other controller is
unaffected and maintains normal operation.
The short-circuit threshold on V
FB2
is based on the smaller
of 0.12V and a fraction of the voltage on the TRACK pin.
This also allows V
OUT2
to start up and track V
OUT1
more
easily. Note that if V
OUT1
is truly short-circuited
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(Refer to Functional Diagram)
(V
OUT1
= V
FB1
= 0V), then the LTC3736 will try to regulate
V
OUT2
to 0V if a resistor divider on V
OUT1
is connected to
the TRACK pin.
Output Overvoltage Protection
As a further protection, the overvoltage comparator (OV)
guards against transient overshoots, as well as other more
serious conditions that may overvoltage the output. When
the feedback voltage on the V
FB
pin has risen 13.33%
above the reference voltage of 0.6V, the external P-chan-
nel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
Frequency Selection and Phase-Locked Loop
(PLLLPF and SYNC/FCB Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage.
The switching frequency of the LTC3736’s controllers can
be selected using the PLLLPF pin.
If the SYNC/FCB is not being driven by an external clock
source, the PLLLPF can be floated, tied to V
IN
or tied to
SGND to select 550kHz, 750kHz or 300kHz respectively.
A phase-locked loop (PLL) is available on the LTC3736 to
synchronize the internal oscillator to an external clock
source that connected to the SYNC/FCB pin. In this case,
a series RC should be connected between the PLLLPF pin
and SGND to serve as the PLL’s loop filter. The LTC3736
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of controller 1’s external P-channel
MOSFET to the rising edge of the synchronizing signal.
Thus, the turn-on of controller 2’s external P-channel
MOSFET is 180 degrees out of phase with the rising edge
of the external clock source.
The typical capture range of the LTC3736’s phase-locked
loop is from approximately 200kHz to 1MHz, and is
guaranteed over temperature to be between 250kHz and
850kHz. In other words, the LTC3736’s PLL is guaranteed
to lock to an external clock source whose frequency is
between 250kHz and 850kHz.
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LTC3736
3736fa
OPERATIO
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(Refer to Functional Diagram)
Dropout Operation
When the input supply voltage (V
IN
) decreases towards
the output voltage, the rate of change of the inductor
current while the external P-channel MOSFET is on (ON
cycle) decreases. This reduction means that the P-channel
MOSFET will remain on for more than one oscillator cycle
if the inductor current has not ramped up to the threshold
set by the EAMP on the I
TH
pin. Further reduction in the
input supply voltage will eventually cause the P-channel
MOSFET to be turned on 100%; i.e., DC. The output
voltage will then be determined by the input voltage minus
the voltage drop across the P-channel MOSFET and the
inductor.
Undervoltage Lockout
To prevent operation of the external MOSFETs below safe
input voltage levels, an undervoltage lockout is incorporated
in the LTC3736. When the input supply voltage (V
IN
) drops
below 2.3V, the external P- and N-channel MOSFETs and
all internal circuitry are turned off except for the undervolt-
age block, which draws only a few microamperes.
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG1 and IPRG2 Pins)
When a controller is operating below 20% duty cycle, the
peak current sense voltage (between the SENSE
+
and SW
pins) allowed across the external P-channel MOSFET is
determined by:
=
()
V
AV V
SENSE MAX
ITH
()
–.07
10
where A is a constant determined by the state of the IPRG
pins. Floating the IPRG pin selects A = 1; tying IPRG to V
IN
selects A = 5/3; tying IPRG to SGND selects A = 2/3. The
maximum value of V
ITH
is typically about 1.98V, so the
maximum sense voltage allowed across the external
P-channel MOSFET is 125mV, 85mV or 204mV for the
three respective states of the IPRG pin. The peak sense
voltages for the two controllers can be independently
selected by the IPRG1 and IPRG2 pins.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peak sense voltage by a scale factor given by the curve in
Figure 1.
The peak inductor current is determined by the peak sense
voltage and the on-resistance of the external P-channel
MOSFET:
I
V
R
PK
SENSE MAX
DS ON
=
()
()
DUTY CYCLE (%)
10
SF = I/I
MAX
(%)
60
80
110
100
90
3736 F01
40
20
50
70
90
30
10
0
30
50
70
200
40
60
80
100
Figure 1. Maximum Peak Current vs Duty Cycle
Power Good (PGOOD) Pin
A window comparator monitors both feedback voltages
and the open-drain PGOOD output pin is pulled low when
either or both feedback voltages are not within ±10% of
the 0.6V reference voltage. PGOOD is low when the
LTC3736 is shut down or in undervoltage lockout.
2-Phase Operation
Why the need for 2-phase operation? Until recently, con-
stant frequency dual switching regulators operated both
controllers in phase (i.e., single phase operation). This
means that both topside MOSFETs (P-channel) are turned
on at the same time, causing current pulses of up to twice
the amplitude of those from a single regulator to be drawn
from the input capacitor. These large amplitude pulses
increase the total RMS current flowing in the input capaci-
tor, requiring the use of larger and more expensive input
capacitors, and increase both EMI and power losses in the
input capacitor and input power supply.

LTC3736EGN#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2-Phase Synch Controller w/ Tracking
Lifecycle:
New from this manufacturer.
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