P9038 DATASHEET
P9038 August 1, 2016 5 ©2016 Integrated Device Technology, Inc.
NOTES:
1. 10m 1% or better sense resistor is required to meet the FOD specification
2. This current is the sum of the input currents for REG_IN, IN, ISNSP_IN, ISNSN_IN, and EN_B.
3. 3.For internal use - do not externally load.
4. Guaranteed by Design.
5. Any of the GPIO pins is capable of sourcing 8mA. The GPIO connected to the ADC have a max operating input voltage of 2.4V to prevent saturation of the ADC.
VDP/DM_LGCLO Logic Low 0.8 V
RDP_DWN Pull-down Resistance 14.25 19.5 24.8 k
CI Input Capacitance
Dm pin, Switch Open 4.5 5 pF
Dp pin, Switch Open 4.5 5 pF
IILK Input Leakage
Dm pin, Switch Open V = 5.0 -1 +1 A
Dp pin, Switch Open V = 5.0 -1+1A
SCL, SDA (I
2
C Interface)
f
SCL_MSTR1
f
SCL_MSTR1
f
SCL_MSTR1
f
SCL_MSTR1
f
SCL_MSTR1
f
SCL_MSTR1
f
SCL_MSTR1
f
SCL_MSTR2
f
SCL_MSTR2
f
SCL_MSTR2
f
SCL_MSTR2
f
SCL_MSTR2
f
SCL_MSTR2
f
SCL_MSTR2
f
SCL_SLV
Clock Frequency P9038 as Slave 0 400 kHz
t
HD,STA
Hold Time (Repeated)
for START Condition
0.6 µs
t
HD:DAT
Data Hold Time I
2
C-bus Devices 10 ns
t
LOW
Clock Low Period 1.3 µs
t
HIGH
Clock High Period 0.6 µs
t
SU:STA
Set-up Time for
Repeated START
Condition
100 ns
t
BUF
Bus Free Time between
STOP and START
Condition
1.3 µs
C
B
Capacitive Load for
each Bus Line
100 pF
C
BIN
SCL, SDA
Input Capacitance
5
5pF
V
IL
Input Threshold Low 0.4 V
V
IH
Input Threshold High 1.4 V
I
LKG
Input Leakage Current V = 0V & 5V -1.0 1.0 µA
V
OL
Output Logic Low (SDA) I = 2mA 0.25 V
Symbol Description Conditions Min Typ Max Units