LTC4290/LTC4271
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Invalid Type 2 Class Combinations
The 802.3at specification defines a Type 2 PD class
signature as two consecutive Class 4 results; a Class 4
followed by a Class 0-3 is not a valid signature. In AUTO
pin mode, the LTC4290/LTC4271 will power a detected
PD regardless of the classification results, with one excep-
tion: if the PD
presents an invalid Type 2 signature (Class
4 followed by Class 0 to 3), the LTC4290/LTC4271 will
not provide power and will restart the detection process.
To aid in diagnosis, the Port Status register will always
report the results of the last class pulse, so an invalid
Class 4–Class 2 combination would report a second class
pulse was run in the High Power Status register (which
implies that the first cycle found class 4), and Class 2 in
the Port Status register.
POWER CONTROL
The primary function of the LTC4290/LTC4271 is to
control the delivery of power to the PSE port. It does this
by controlling the gate drive voltage of an external power
MOSFET while monitoring the current via an external sense
resistor and the output voltage at the OUT pin. This circuitry
serves to couple the raw V
EE
input supply to the port in
a controlled manner that satisfies the PDs power needs
while minimizing both power dissipation in the MOSFET
and disturbances on the V
EE
backplane.
Inrush Control
Once the command has been given to turn on a port, the
LTC4290/LTC4271 ramps up the GATE pin of that port’s
external MOSFET in a controlled manner. Under normal
power-up circumstances, the MOSFET gate will rise until
the port current reaches the inrush current limit level
(typically 425mA), at which point the GATE pin will be
servoed to maintain the specified I
INRUSH
current. During
this inrush period, a timer (t
START
) runs. When output
charging is complete, the port current will fall and the GATE
pin will be allowed to continue rising to fully enhance the
MOSFET and minimize its on-resistance. The final V
GS
is
APPLICATIONS INFORMATION
nominally 12V. The inrush period is maintained until the
t
START
timer expires. At this time if the inrush current limit
level is still exceeded, the port will be turned back off and
a t
START
fault reported.
Current Limit
Each LTC4290/LTC4271 port includes two current limit-
ing thresholds (I
CUT
and I
LIM
), each with a corresponding
timer (t
CUT
and t
LIM
). Setting the I
CUT
and I
LIM
thresholds
depends on several factors: the class of the PD, the volt-
age of the main supply (V
EE
), the type of PSE (Type 1 or
Type 2), the sense resistor (0.5Ω or 0.25Ω), the SOA of
the MOSFET, and whether or not the system is required
to enforce class current levels.
Per the IEEE specification, the LTC4290/LTC4271 will al-
low the port current to exceed I
CUT
for a limited period of
time before removing power from the port, whereas it will
actively control the MOSFET gate drive to keep the port
current below I
LIM
. The port does not take any action to
limit the current when only the I
CUT
threshold is exceeded,
but does start the t
CUT
timer. If the current drops below
the I
CUT
current threshold before its timer expires, the
t
CUT
timer counts back down, but at 1/16 the rate that it
counts up. If the t
CUT
timer reaches 60ms (typical) the
port is turned off and the port t
CUT
fault is set. This allows
the current limit circuitry to tolerate intermittent overload
signals with duty cycles below about 6%; longer duty cycle
overloads will turn the port off.
The I
LIM
current limiting circuit is always enabled and ac-
tively limiting port current. The t
LIM
timer is enabled only
when the t
LIM
Enable bit is set. This allows t
LIM
to be set
to a shorter value than t
CUT
to provide more aggressive
MOSFET protection and turn off a port before MOSFET
damage can occur. The t
LIM
timer starts when the I
LIM
threshold is exceeded. When the t
LIM
timer reaches 12ms
(typical) the port is turned off and the port t
LIM
fault is
set. When the t
LIM
Enable bit is disabled t
LIM
behaviors
are tracked by the t
CUT
timer, which counts up during both
I
LIM
and I
CUT
events.
