LTC4290/LTC4271
25
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For more information www.linear.com/LTC4290
APPLICATIONS INFORMATION
Register Description
For information on serial bus usage and device configura-
tion and status, refer to the LTC4271 Software Program-
ming documentation.
ISOLATION REQUIREMENTS
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface de-
vice. However, network segments are not required to be
isolated from each other, provided that the segments are
connected to devices residing within a single building on
a single power distribution system.
For simple devices such as small PoE switches, the isola-
tion requirement can be met by using an isolated main
power supply for the entire device. This strategy can be
used if the device has no electrically conducting ports
other than twisted-pair Ethernet. In this case, the SDAIN
and SDAOUT pins can be tied together and will act as a
standard I
2
C/SMBus SDA pin.
If the device is part of a larger system, contains additional
external non-Ethernet ports, or must be referenced to
protective ground for some other reason, the Power over
Ethernet subsystem must be electrically isolated from the
rest of the system.
The LTC4290/LTC4271 chipset simplifies PSE isolation by
allowing the LTC4271 chip to reside on the non-isolated
side. There it can receive power from the main logic sup-
ply and connect directly to the I
2
C/SMBus bus. Isolation
between the LTC4271 and LTC4290 is implemented using
a proprietary transformer-based communication protocol.
Additional details are provided in the Serial Bus Isolation
section of this data sheet.
EXTERNAL COMPONENT SELECTION
Power Supplies and Bypassing
The LTC4290/LTC4271 requires two supply voltages to
operate. V
DD
requires 3.3V (nominally) relative to DGND.
V
EE
requires a negative voltage of between –45V and
–57
V for Type 1 PSEs, –51V to –57V for Type 2 PSEs,
or –54.75V to –57V for LTPoE
++
PSEs, relative to AGND.
Digital Power Supply
V
DD
provides digital power for the LTC4271 processor,
and draws a maximum of 15mA. A ceramic decoupling
cap of at least 0.1μF should be placed from V
DD
to DGND,
as close as practical to each LTC4271 chip. A 1.8V core
voltage supply is generated internally and requires a 1µF
ceramic decoupling cap between the CAP1 pin and DGND.
In the LTC4290/LTC4271, V
DD
should be delivered by the
host controller’s non-isolated 3.3V supply. To maintain
required isolation AGND and DGND must not be con-
nected in any way.
Main PoE Power Supply
V
EE
is the main isolated PoE supply that provides power
to the PDs. Because it supplies a relatively large amount
of power and is subject to significant current transients,
it requires more design care than a simple logic supply.
For minimum IR loss and best system efficiency, set V
EE
near maximum amplitude (57V), leaving enough margin
to account for transient over or undershoot, temperature
drift, and the line regulation specifications of the particular
power supply used.
Bypass capacitance between AGND and V
EE
is very im-
portant for reliable operation. If a short circuit occurs at
one of the output ports it can take as long as 1μs for the
LTC4290 to begin regulating the current. During this time
the current is limited only by the small impedances in the
circuit and a high current spike typically occurs, causing a
