LTC2440CGN#PBF Datasheet LTC2440CGN#PBF, LTC2440IGN#PBF | P10-P12

LTC2440

2440fe

For more information www.linear.com/LTC2440

APPLICATIONS INFORMATION

Initially, the LTC2440 performs a conversion. Once the

conversion is complete, the device enters the sleep state.

While in this sleep state, power consumption is reduced

below 10µA. The part remains in the sleep state as long as

CS is HIGH. The conversion result is held indefinitely in a

static shift register while the converter is in the sleep state.

Once CS is pulled LOW, the device begins outputting the

conversion result. There is no latency in the conversion

result. The data output corresponds to the conversion

just performed. This result is shifted out on the serial data

out pin (SDO) under the control of the serial clock (SCK).

Data is updated on the falling edge of SCK allowing the

user to reliably latch data on the rising edge of SCK (see

Figure 3). The data output state is concluded once 32-bits

are read out of the ADC or when CS is brought HIGH. The

device automatically initiates a new conversion and the

cycle repeats.

Through timing control of the CS, SCK and EXT pins,

the LTC2440 offers several flexible modes of operation

(internal or external SCK). These various modes do not

require programming configuration registers; moreover,

they do not disturb the cyclic operation described above.

These modes of operation are described in detail in the

Serial Interface Timing Modes section.

Ease of Use

The LTC2440 data output has no latency, filter settling

delay or redundant data associated with the conversion

cycle. There is a one-to-one correspondence between the

conversion and the output data. Therefore, multiplexing

multiple analog voltages is easy. Speed/resolution adjust

ments may be made seamlessly between two conversions

without settling errors.

The LT

C2440

performs offset and full-scale calibrations

every conversion cycle. This calibration is transparent to

the user and has no effect on the cyclic operation described

above. The advantage of continuous calibration is extreme

stability of offset and full-scale readings with respect to

time, supply voltage change and temperature drift.

Power-Up Sequence

The LTC2440 automatically enters an internal reset state

when the power supply voltage V

drops below approxi-

mately 2.2V. This feature guarantees the integrity of the

conversion result and of the serial inter

face mode selection.

When the V

voltage rises above this critical threshold, the

converter creates an internal power-on-reset (POR) signal

with a duration of approximately 0.5ms. The POR signal

clears all internal registers. Following the POR signal, the

LTC2440 starts a normal conversion cycle and follows the

succession of states described above. The first conversion

result following POR is accurate within the specifications

of the device if the power supply voltage is restored within

the operating range (4.5V to 5.5V) before the end of the

POR time interval.

Reference Voltage Range

This converter accepts a truly differential external reference

voltage. The absolute/common mode voltage specification

for the REF

and REF

–

pins covers the entire range from

GND to V

. For correct converter operation, the REF

must always be more positive than the REF

–

pin.

The LTC2440 can accept a differential reference voltage

from 0.1V to V

. The converter output noise is determined

by the thermal noise of the front-end circuits, and as such,

its value in microvolts is nearly constant with reference

voltage. A decrease in reference voltage will not signifi

cantly improve the converter’s effective resolution. On the

other hand, a reduced reference voltage will improve the

converter’s overall INL per

formance.

Input Voltage Range

The analog input is truly differential with an absolute/com

mon mode range for the IN

and IN

–

input pins extending

from GND – 0.3V to V

+ 0.3V. Outside these limits, the

ESD protection devices begin to turn on and the errors

due to input leakage current increase rapidly. Within these

limits, the LTC2440 converts the bipolar differential input

signal, V

= IN

– IN

–

, from –FS = –0.5 • V

REF

to +FS =

0.5 • V

REF

where V

REF

= REF

– REF

–

. Outside this range,

LTC2440

2440fe

For more information www.linear.com/LTC2440

APPLICATIONS INFORMATION

Figure 3. Output Data Timing

the converter indicates the overrange or the underrange

condition using distinct output codes.

Output Data Format

The LTC2440 serial output data stream is 32-bits long.

The first 3-bits represent status information indicating

the sign and conversion state. The next 24-bits are the

conversion result, MSB first. The remaining 5-bits are

sub LSBs beyond the 24-bit level that may be included in

averaging or discarded without loss of resolution. In the

case of ultrahigh resolution modes, more than 24 effective

bits of performance are possible (see Table 3). Under these

conditions, sub LSBs are included in the conversion result

and represent useful information beyond the 24-bit level.

The third and fourth bit together are also used to indicate

an underrange condition (the differential input voltage is

below –FS) or an overrange condition (the differential input

voltage is above +FS). For input conditions in excess of

twice full scale (|V

| ≥ V

REF

), the converter may indicate

either overrange or underrange. Once the input returns to

the normal operating range, the conversion result is im

mediately accurate within the specifications of the device.

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 30 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 29 (third output bit) is the conversion result sign

indicator (SIG). If V

is >0, this bit is HIGH. If V

is <0,

this bit is LOW.

Bit 28 (fourth output bit) is the most significant bit (MSB) of

the result. This bit in conjunction with Bit 29 also provides

the underrange or overrange indication. If both Bit 29 and

Bit 28 are HIGH, the differential input voltage is above +FS.

If both Bit 29 and Bit 28 are LOW, the differential input

voltage is below –FS.

The function of these bits is summarized in Table 1.

Table 1. LTC2440 Status Bits

Input Range

Bit 31

EOC

Bit 30

DMY

Bit 29

SIG

Bit 28

MSB

≥ 0.5 • V

REF

0 0 1 1

0V ≤ V

< 0.5 • V

REF

0 0 1 0

–0.5 • V

REF

≤ V

< 0V 0 0 0 1

< –0.5 • V

REF

0 0 0 0

Bits ranging from 28 to 5 are the 24-bit conversion result

MSB first.

Bit 5 is the Least Significant Bit (LSB).

Bits ranging from 4 to 0 are sub LSBs below the 24-bit

level. Bits 4 to bit 0 may be included in averaging or dis

carded without loss of resolution.

Data is shifted out of the SDO pin under control of the

serial clock (SCK), see Figure 3. Whenever

is HIGH,

SDO remains high impedance.

In order to shift the conversion result out of the device,

CS must first be driven LOW. EOC is seen at the SDO pin

of the device once CS is pulled LOW. EOC changes real

time from HIGH to LOW at the completion of a conversion.

This signal may be used as an interrupt for an external

microcontroller. Bit 31 (EOC) can be captured on the first

rising edge of SCK. Bit 30 is shifted out of the device on

the first falling edge of SCK. The final data bit (Bit 0) is

MSBSIG“0”

1 2 3 4 5 26 27 32

BIT 0BIT 27 BIT 5

LSB

BIT 28BIT 29BIT 30

SDO

SCK

BUSY

EOC

BIT 31

SLEEP DATA OUTPUT CONVERSION

2440 F03

Hi-Z

LTC2440

2440fe

For more information www.linear.com/LTC2440

APPLICATIONS INFORMATION

shifted out on the falling edge of the 31st SCK and may

be latched on the rising edge of the 32nd SCK pulse. On

the falling edge of the 32nd SCK pulse, SDO goes HIGH

indicating the initiation of a new conversion cycle. This

bit serves as EOC (Bit 31) for the next conversion cycle.

Table 2 summarizes the output data format.

As long as the voltage on the IN

and IN

–

pins is main-

tained within the –0.3V to (V

+ 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage V

from –FS = –0.5 • V

REF

+FS = 0.5 • V

REF

. For differential input voltages greater

than +FS, the conversion result is clamped to the value

corresponding to the +FS + 1LSB. For differential input

voltages below –FS, the conversion result is clamped to

the value corresponding to –FS – 1LSB.

SERIAL INTERFACE PINS

The LTC2440 transmits the conversion results and receives

the start of conversion command through a synchronous

2-wire, 3-wire or 4-wire interface. During the conversion

and sleep states, this interface can be used to assess

the converter status and during the data output state it

is used to read the conversion result and program the

speed/resolution.

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 13) is used to

synchronize the data transfer. Each bit of data is shifted

out the SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is an

output and the LTC2440 creates its own serial clock. In

the External SCK mode of operation, the SCK pin is used

as input. The internal or external SCK mode is selected

by tying EXT (Pin 10) LOW for external SCK and HIGH

for internal SCK.

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 12), provides the

result of the last conversion as a serial bit stream (MSB

first) during the data output state. In addition, the SDO

pin is used as an end of conversion indicator during the

conversion and sleep states.

When CS (Pin 11) is HIGH, the SDO driver is switched

to a high impedance state. This allows sharing the serial

interface with other devices. If CS is LOW during the

convert or sleep state, SDO will output EOC. If CS is LOW

during the conversion phase, the EOC bit appears HIGH

on the SDO pin. Once the conversion is complete, EOC

goes LOW. The device remains in the sleep state until the

first rising edge of SCK occurs while CS = LOW.

Table 2. LTC2440 Output Data Format

Differential Input Voltage

Bit 31

EOC

Bit 30

DMY

Bit 29

SIG

Bit 28

MSB

Bit 27

Bit 26

Bit 25

…

Bit 0

* ≥ 0.5 • V

REF

** 0 0 1 1 0 0 0 … 0

0.5 • V

REF

** – 1LSB 0 0 1 0 1 1 1 … 1

0.25 • V

REF

** 0 0 1 0 1 0 0 … 0

0.25 • V

REF

** – 1LSB 0 0 1 0 0 1 1 … 1

0 0 0 1 0 0 0 0 … 0

–1LSB 0 0 0 1 1 1 1 … 1

–0.25 • V

REF

** 0 0 0 1 1 0 0 … 0

–0.25 • V

REF

** – 1LSB 0 0 0 1 0 1 1 … 1

–0.5 • V

REF

** 0 0 0 1 0 0 0 … 0

* < –0.5 • V

REF

** 0 0 0 0 1 1 1 … 1

*The differential input voltage V

= IN

– IN

–

. **The differential reference voltage V

REF

= REF

– REF

–

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LTC2440CGN#PBF

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 24-Bit Diff Input High Speed Delta Sigma ADC

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LTC2440CGN#PBF

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