LTC2440
19
2440fe
For more information www.linear.com/LTC2440
APPLICATIONS INFORMATION
Figure 10. Internal Serial Clock, Continuous Operation
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversampling ratio, the LTC2440 significantly
simplifies antialiasing filter requirements.
The LTC2440’s speed/resolution is determined by the
over sample ratio (OSR) of the on-chip digital filter. The
OSR ranges from 64 for 3.5kHz output rate to 32,768 for
6.9Hz output rate. The value of OSR and the sample rate f
S
determine the filter characteristics of the device. The first
NULL of the digital filter is at f
N
and multiples of f
N
where
f
N
= f
S
/OSR, see Figure 11 and Table 5. The rejection at
the frequency f
N
±14% is better than 80dB, see Figure 12.
If f
O
is grounded, f
S
is set by the on-chip oscillator at
1.8MHz (over supply and temperature variations). At an
OSR of 32,768, the first NULL is at f
N
= 55Hz and the no
latency output rate is f
N
/8 = 6.9Hz. At the maximum OSR,
Figure 11. LTC2440 Normal Mode Rejection (Internal Oscillator)
SDO
BUSY
SCK
(INTERNAL)
CS
LSB
24
MSBSIG
BIT 5 BIT 0BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT CONVERSIONCONVERSION
2410 F10
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
V
CC
f
O
REF
+
REF
SCK
BUSY
IN
+
IN
SDO
GND
CS
EXT
2
14
3
4
13
5
6
12
1, 8, 9, 16
11
10
15
SDI
V
CC
7
REFERENCE VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
1µF
4.5V TO 5.5V
LTC2440
2-WIRE
SPI INTERFACE
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2µV NOISE, 880Hz OUTPUT RATE
V
CC
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–60
–40
0
180
2440 F11
–80
–100
60 120 240
–120
–140
–20
NORMAL MODE REJECTION (dB)
LTC2440
20
2440fe
For more information www.linear.com/LTC2440
APPLICATIONS INFORMATION
the noise performance of the device is 200nV
RMS
with
better than 80dB rejection of 50Hz ±2% and 60Hz ±2%.
Since the OSR is large (32,768) the wide band rejection
is extremely large and the antialiasing requirements are
simple. The first multiple of f
S
occurs at 55Hz • 32,768 =
1.8MHz, see Figure 13.
The first NULL becomes f
N
= 7.04kHz with an OSR of 256
(an output rate of 880Hz) and f
O
grounded. While the NULL
has shifted, the sample rate remains constant. As a result
of constant modulator sampling rate, the linearity, offset
and full-scale performance remains unchanged as does
the first multiple of f
S
.
Figure 12. LTC2440 Normal Mode Rejection (Internal Oscillator) Figure 13. LTC2440 Normal Mode Rejection (Internal Oscillator)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
47
–140
NORMAL MODE REJECTION (dB)
–130
–120
–110
–100
51 55
59
63
2440 F12
–90
–80
49 53
57
61
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–60
–40
0
1440 F13
–80
–100
1000000 2000000
–120
1.8MHz
–140
–20
NORMAL MODE REJECTION (dB)
REJECTION > 120dB
Table 5. OSR vs Notch Frequency (f
N
) with Internal Oscillator
OSR NOTCH (f
N
)
64 28.16kHz
128 14.08kHz
256 7.04kHz
512 3.52kHz
1024 1.76kHz
2048 880Hz
4096 440Hz
8192 220Hz
16384 110Hz
32768* 55Hz
*Simultaneous 50/60 rejection
LTC2440
21
2440fe
For more information www.linear.com/LTC2440
APPLICATIONS INFORMATION
Figure 14. LTC2440 Normal Mode Rejection
(External Oscillator at 90kHz)
The sample rate f
S
and NULL f
N
, my also be adjusted by
driving the f
O
pin with an external oscillator. The sample
rate is f
S
= f
EOSC
/5, where f
EOSC
is the frequency of the
clock applied to f
O
. Combining a large OSR with a reduced
sample rate leads to notch frequencies f
N
near DC while
maintaining simple antialiasing requirements. A 100kHz
clock applied to f
O
results in a NULL at 0.6Hz plus all
harmonics up to 20kHz, see Figure 14. This is useful in
applications requiring digitalization of the DC component
of a noisy input signal and eliminates the need of placing
a 0.6Hz filter in front of the ADC.
An external oscillator operating from 100kHz to 12MHz can
be implemented using the LTC1799 (resistor set SOT-23
oscillator), see Figure 22. By floating pin 4 (DIV) of the
LTC1799, the output oscillator frequency is:
f MHz
k
R
OSC
SET
=
10
10
10
The normal mode rejection characteristic shown in
Figure 14 is achieved by applying the output of the LTC1799
(with R
SET
= 100k) to the f
O
pin on the LTC2440 with SDI
tied HIGH (OSR = 32768).
Reduced Power Operation
In addition to adjusting the speed/resolution of the
LTC2440, the speed/resolution/power dissipation may
also be adjusted using the automatic sleep mode. During
the conversion cycle, the LTC2440 draws 8mA supply
current independent of the programmed speed. Once the
conversion cycle is completed, the device automatically
enters a low power sleep state drawing 8µA. The device
remains in this state as long as CS is HIGH and data is not
shifted out. By adjusting the duration of the sleep state
(hold CS HIGH longer) and the duration of the conversion
cycle (programming OSR) the DC power dissipation can
be reduced, see Figure 16.
For example, if the OSR is programmed at the fastest rate
(OSR = 64, t
CONV
= 0.285ms) and the sleep state is 10ms,
the effective output rate is approximately 100Hz while the
average supply current is reduced to 240µA. By further
extending the sleep state to 100ms, the effective output
rate of 10Hz draws on average 30µA. Noise, power, and
speed can be optimized by adjusting the OSR (Noise/
Speed) and sleep mode duration (Power).
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–40
–20
0
8
2440 F14
–60
–80
2 4 6 10
–100
–120
–140
NORMAL MODE REJECTION (dB)

LTC2440CGN#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 24-Bit Diff Input High Speed Delta Sigma ADC
Lifecycle:
New from this manufacturer.
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