LTC2440
8
2440fe
For more information www.linear.com/LTC2440
PIN FUNCTIONS
GND (Pins 1, 8, 9, 16): Ground. Multiple ground pins
internally connected for optimum ground current flow
and V
CC
decoupling. Connect each one of these pins to a
ground plane through a low impedance connection. All four
pins must be connected to ground for proper operation.
V
CC
(Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
REF
+
(Pin 3), REF
–
(Pin 4): Differential Reference Input.
The voltage on these pins can have any value between
GND and V
CC
as long as the reference positive input, REF
+
,
is maintained more positive than the reference negative
input, REF
–
, by at least 0.1V.
IN
+
(Pin 5), IN
–
(Pin 6): Differential Analog Input. The
voltage on these pins can have any value between GND
– 0.3V and V
CC
+ 0.3V. Within these limits the converter
bipolar input range (V
IN
= IN
+
– IN
–
) extends from –0.5 •
(V
REF
) to 0.5 • (V
REF
). Outside this input range the converter
produces unique overrange and underrange output codes.
SDI (Pin 7): Serial Data Input. This pin is used to select
the speed/resolution of the converter. If SDI is grounded
(pin compatible with LTC2410) the device outputs data at
880Hz with 21 bits effective resolution. By tying SDI HIGH,
the converter enters the ultralow noise mode (200nV
RMS
)
with simultaneous 50/60Hz rejection at 6.9Hz output rate.
SDI may be driven logic HIGH or LOW anytime during the
conversion or sleep state in order to change the speed/
resolution. The conversion immediately following the data
output cycle will be valid and performed at the newly se
-
lected output rate/resolution. SDI may also be programmed
by a serial input data stream under control of SCK during
the data output cycle. One of ten speed/resolution ranges
(from 6.9Hz/200nV
RMS
to 3.5kHz/21µV
RMS
) may be se-
lected. The first conversion following a new selection is
valid and performed at the newly selected speed/resolution.
EXT
(Pin 10): Internal/External SCK Selection Pin. This pin
is used to select internal or external SCK for outputting
data. If EXT is tied low (pin compatible with the LTC2410),
the device is in the external SCK mode and data is shifted
out the device under the control of a user applied serial
clock. If EXT is tied high, the internal serial clock mode
is selected. The device generates its own SCK signal and
outputs this on the SCK pin. A framing signal BUSY (Pin 15)
goes low indicating data is being output.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
CC
) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data Output
period. In External Serial Clock Operation mode, SCK is
used as digital input for the external serial interface clock
during the Data Output period. The Serial Clock Operation
mode is determined by the logic level applied to the EXT pin.
f
O
(Pin 14): Frequency Control Pin. Digital input that con-
trols the internal conversion clock. When f
O
is connected
to V
CC
or GND, the converter uses its internal oscillator.
BUSY (Pin 15): Conversion in Progress Indicator. For
compatibility with the LTC2410, this pin should not be
tied to ground. This pin is HIGH while the conversion
is in progress and goes LOW indicating the conversion
is complete and data is ready. It remains low during the
sleep and data output states. At the conclusion of the data
output state, it goes HIGH indicating a new conversion
has begun.
