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AD7665ASTZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
REV.
AD7665
–18–
t
3
BUSY
CS
,
RD
CNVST
SYNC
SCLK
SDOUT
t
28
t
29
t
14
t
18
t
19
t
20
t
21
t
24
t
26
t
27
t
23
t
22
t
16
t
15
123 141516
D15 D14
D2 D1 D0
X
EXT/
INT
= 0
RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t
25
t
30
Figure 17. Master Serial Data Timing for Reading (Read after Convert)
EXT/INT = 0
RDC/SDIN = 1 INVSCLK = INVSYNC = 0
t
3
t
1
t
17
t
14
t
19
t
20
t
21
t
24
t
26
t
25
t
27
t
23
t
22
t
16
t
15
D15 D14 D2 D1 D0X
12 3 141516
t
18
BUSY
SYNC
SCLK
SDOUT
CS, RD
CNVST
Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
C
REV.
AD7665
–19–
CS
SCLK
SDOUT
D15 D14 D1
D0
D13
X15 X14 X13 X1 X0 Y15 Y14
BUSY
SDIN
INVSCLK = 0
t
35
t
36
t
37
t
31
t
32
t
16
t
33
t
34
X15 X14
X
123 1415161718
EXT/INT = 1
RD = 0
Figure 19. Slave Serial Data Timing for Reading (Read after Convert)
In Read-during-Conversion Mode, the serial clock and data toggle
at appropriate instants, which minimizes potential feedthrough
between digital activity and the critical conversion decisions.
In Read-after-Conversion Mode, it should be noted that unlike
in other modes, the signal BUSY returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
SLAVE SERIAL INTERFACE
External Clock
The AD7665 is configured to accept an externally supplied serial
data clock on the SCLK pin when the EXT/INT pin is held
HIGH. In this mode, several methods can be used to read the
data. The external serial clock is gated by CS and the data are
output when both CS and RD are LOW. Thus, depending on CS,
the data can be read after each conversion or during the follow-
ing conversion. The external clock can be either a continuous or
discontinuous clock. A discontinuous clock can be either normally
HIGH or normally LOW when inactive. Figures 19 and 21 show
the detailed timing diagrams of these methods.
While the AD7665 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is particu-
larly important during the second half of the conversion phase
because the AD7665 provides error correction circuitry that can
correct for an improper bit decision made during the first half of
the conversion phase. For this reason, it is recommended that
when an external clock is being provided, it is a discontinuous clock
that is toggling only when BUSY is LOW or, more importantly,
that does not transition during the latter half of BUSY HIGH.
External Discontinuous Clock Data Read after Conversion
Though the maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
LOW, the result of this conversion can be read while both CS
and RD are LOW. The data is shifted out, MSB first, with
16 clock pulses and is valid on both the rising and falling edge
of the clock.
Among the advantages of this method, the conversion performance
is not degraded because there are no voltage transients on the
digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up
to 40 MHz, which accommodates both slow digital host interface
and the fastest serial reading.
Finally, in this mode only, the AD7665 provides a “daisy-chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when desired as, for instance, in
isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 20. Simultaneous sampling is possible by using a com-
mon CNVST signal. It should be noted that the RDC/SDIN
input is latched on the opposite edge of SCLK of the one used
to shift out the data on SDOUT. Therefore, the MSB of the
“upstream” converter just follows the LSB of the “downstream”
converter on the next SCLK cycle.
CNVST
CS
SCLK
SDOUTRDC/SDIN
BUSYBUSY
DATA
OUT
AD7665
#1
(DOWNSTREAM)
BUSY
OUT
CNVST
CS
SCLK
AD7665
#2
(UPSTREAM)
RDC/SDIN SDOUT
SCLK IN
CS IN
CNVST IN
Figure 20. Two AD7665s in a Daisy-Chain Configuration
C
REV.
AD7665
–20–
CNVST
SDOUT
SCLK
D1 D0X D15 D14 D13
12 3 141516
t
3
t
35
t
36
t
37
t
31
t
32
t
16
BUSY
INVSCLK = 0
CS, RD
EXT/INT = 1
RD = 0
Figure 21. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
External Clock Data Read during Conversion
Figure 21 shows the detailed timing diagrams of this method. Dur-
ing a conversion, while both CS and RD are LOW, the result of
the previous conversion can be read. The data is shifted out, MSB
first, with 16 clock pulses and is valid on both the rising and
falling edge of the clock. The 16 bits have to be read before the
current conversion is complete. If that is not done, RDERROR
is pulsed HIGH and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain feature
in this mode, and RDC/SDIN input should always be tied either
HIGH or LOW.
To reduce performance degradation due to digital activity, a fast
discontinuous clock, at least 25 MHz when Impulse Mode is
used or 40 MHz when Normal or Warp Mode is used, is recom-
mended to ensure that all the bits are read during the first half
of the conversion phase. It is also possible to begin to read the
data after conversion and continue to read the last bits even after
a new conversion has been initiated. That allows the use of a slower
clock speed like 10 MHz in Impulse Mode, 12 MHz in Normal
Mode, and 15 MHz in Warp Mode.
MICROPROCESSOR INTERFACING
The AD7665 is ideally suited for traditional dc measurement
applications supporting a microprocessor and ac signal processing
applications interfacing to a digital signal processor. The AD7665
is designed to interface with either a parallel 8-bit or 16-bit wide
interface or with a general-purpose Serial Port or I/O Ports on a
microcontroller. A variety of external buffers can be used with
the AD7665 to prevent digital noise from coupling into the ADC.
The following sections illustrate the use of the AD7665 with
an SPI-equipped microcontroller, the ADSP-21065L and
ADSP-218x signal processors.
SPI Interface (MC68HC11)
Figure 22 shows an interface diagram between the AD7665 and
an SPI-equipped microcontroller, such as the MC68HC11. To
accommodate the slower speed of the microcontroller, the
AD7665 acts as a slave device and data must be read after conver-
sion. This mode also allows the daisy-chain feature. The convert
command could be initiated in response to an internal timer
interrupt. The reading of output data, one byte at a time, if
necessary, could be initiated in response to the end-of-conversion
signal (BUSY going LOW) using an interrupt line of the micro-
controller. The serial peripheral interface (SPI) on the MC68HC11
is configured for Master Mode (MSTR) = 1, Clock Polarity Bit
(CPOL) = 0, Clock Phase Bit (CPHA) = 1, and SPI interrupt
enable (SPIE) = 1 by writing to the SPI Control Register (SPCR).
The IRQ is configured for edge-sensitive-only operation
(IRQE = 1 in OPTION register).
IRQ
MC68HC11*
CNVST
AD7665
*
BUSY
CS
MISO/SDI
SCK
I/O PORT
SDOUT
SCLK
INVSCLK
EXT/INT
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
SER/PAR
RD
Figure 22. Interfacing the AD7665 to SPI Interface
ADSP-21065L in Master Serial Interface
As shown in Figure 23, the AD7665 can be interfaced to the
ADSP-21065L using the serial interface in Master Mode without
any glue logic required. This mode combines the advantages of
reducing the wire connections and the ability to read the data during
or after conversion at maximum speed transfer (DIVSCLK[0:1]
both low).
The AD7665 is configured for the Internal Clock Mode
(EXT/INT LOW) and acts therefore as the master device. The
convert command can be generated by either an external low jitter
oscillator or, as shown, by a FLAG output of the ADSP-21065L
or by a frame output TFS of one Serial Port of the ADSP-21065L
that can be used like a timer. The Serial Port on the ADSP-
21065L is configured for external clock (IRFS = 0), rising edge
active (CKRE = 1), external late framed sync signals (IRFS = 0,
LAFS = 1, RFSR = 1), and active HIGH (LRFS = 0). The Serial
Port of the ADSP-21065L is configured by writing to its receive
control register (SRCTL)—see ADSP-2106x SHARC User’s
Manual. Because the Serial Port within the ADSP-21065L will
C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

AD7665ASTZRL

Mfr. #:
Buy AD7665ASTZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16B 570kSPS Bipolar
Lifecycle:
New from this manufacturer.
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