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AD7665ASTZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
REV.
–3–
AD7665
Parameter Conditions Min Typ Max Unit
POWER SUPPLIES (Continued)
Power Dissipation
6, 7
444 kSPS Throughput
8
64 74 mW
100 SPS Throughput
8
15 µW
570 kSPS Throughput
5
93 107 mW
In Power-Down Mode
9
7µW
TEMPERATURE RANGE
10
Specified Performance T
MIN
to T
MAX
–40 +85 °C
NOTES
1
LSB means least significant bit. With the ±5 V input range, one LSB is 152.588 µV.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4
The max should be the minimum of 5.25 V and DVDD + 0.3 V.
5
In Warp Mode.
6
Tested in Parallel Reading Mode.
7
Tested with the 0 V to 5 V range and V
IN
– V
INGND
= 0 V. See Power Dissipation section.
8
In Impulse Mode.
9
With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively.
10
Contact factory for extended temperature range.
Specifications subject to change without notice.
Table I. Analog Input Configuration
Input Voltage Input
Range IND(4R) INC(4R) INB(2R) INA(R) Impedance
1
±4 REF
2
V
IN
INGND INGND REF 5.85 kW
±2 REF V
IN
V
IN
INGND REF 3.41 kW
±REF V
IN
V
IN
V
IN
REF 2.56 kW
0 V to 4 REF V
IN
V
IN
INGND INGND 3.41 kW
0 V to 2 REF V
IN
V
IN
V
IN
INGND 2.56 kW
0 V to REF V
IN
V
IN
V
IN
V
IN
Note 3
NOTES
1
Typical analog input impedance.
2
With REF = 3 V, in this range, the input should be limited to –11 V to +12 V.
3
For this range the input is high impedance.
TIMING SPECIFICATIONS
Parameter
Symbol Min Typ Max Unit
Refer to Figures 11 and 12
Convert Pulsewidth t
1
5ns
Time between Conversions t
2
1.75/2/2.25 Note 1 µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay t
3
30 ns
BUSY HIGH All Modes Except in Master Serial Read after t
4
0.75/1/1.25 µs
Convert Mode (Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay t
5
2ns
End of Conversion to BUSY LOW Delay t
6
10 ns
Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t
7
0.75/1/1.25 µs
Acquisition Time t
8
1µs
RESET Pulsewidth t
9
10 ns
Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t
10
0.75/1/1.25 µs
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay t
11
20 ns
Bus Access Request to DATA Valid t
12
40 ns
Bus Relinquish Time t
13
515ns
(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
C
REV.
AD7665
–4–
TIMING SPECIFICATIONS
(continued)
Parameter
Symbol Min Typ Max Unit
Refer to Figures 17 and 18 (Master Serial Interface Modes)
2
CS LOW to SYNC Valid Delay t
14
10 ns
CS LOW to Internal SCLK Valid Delay t
15
10 ns
CS LOW to SDOUT Delay t
16
10 ns
CNVST LOW to SYNC Delay (Read during Convert) t
17
25/275/525 ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
3
t
18
4ns
Internal SCLK Period
3
t
19
25 40 ns
Internal SCLK HIGH
3
t
20
15 ns
Internal SCLK LOW
3
t
21
9.5 ns
SDOUT Valid Setup Time
3
t
22
4.5 ns
SDOUT Valid Hold Time
3
t
23
2ns
SCLK Last Edge to SYNC Delay
3
t
24
3
CS HIGH to SYNC HI-Z t
25
10 ns
CS HIGH to Internal SCLK HI-Z t
26
10 ns
CS HIGH to SDOUT HI-Z t
27
10 ns
BUSY HIGH in Master Serial Read after Convert
3
t
28
See Table II µs
CNVST LOW to SYNC Asserted Delay t
29
0.75/1/1.25 µs
(Warp Mode/Normal Mode/Impulse Mode)
Master Serial Read after Convert
SYNC Deasserted to BUSY LOW Delay t
30
25 ns
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
External SCLK Setup Time t
31
5ns
External SCLK Active Edge to SDOUT Delay t
32
316ns
SDIN Setup Time t
33
5ns
SDIN Hold Time t
34
5ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
NOTES
1
In Warp Mode only, the maximum time between conversions is 1 ms, otherwise, there is no required maximum time.
2
In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
In Serial Master Read During Convert Mode. See Table II for Master Read after Convert Mode.
Specifications subject to change without notice.
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] 0011
DIVSCLK[0] 0101 Unit
SYNC to SCLK First Edge Delay Minimum t
18
4202020 ns
Internal SCLK Period Minimum t
19
25 50 100 200 ns
Internal SCLK Period Maximum t
19
40 70 140 280 ns
Internal SCLK HIGH Minimum t
20
15 25 50 100 ns
Internal SCLK LOW Minimum t
21
9.5 24 49 99 ns
SDOUT Valid Setup Time Minimum t
22
4.5 22 22 22 ns
SDOUT Valid Hold Time Minimum t
23
243090 ns
SCLK Last Edge to SYNC Delay Minimum t
24
360140 300 ns
BUSY HIGH Width Maximum (Warp) t
28
1.5 2 3 5.25 µs
BUSY HIGH Width Maximum (Normal) t
28
1.75 2.25 3.25 5.5 µs
BUSY HIGH Width Maximum (Impulse) t
28
2 2.5 3.5 5.75 µs
C
REV.
AD7665
–5–
PIN CONFIGURATION
ST-48 and CP-48
36
35
34
33
32
31
30
29
28
27
26
25
13 14
15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48
47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
NC
BYTESWAP
OB/2C
WARP
IMPULSE
NC = NO CONNECT
SER/PAR
D0
D1
D2/DIVSCLK[0]
BUSY
D15
D14
D13
AD7665
D3/DIVSCLK[1]
D12
D4/EXT/INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OVDD
DVDD
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERROR
NC
NC
NC
NC
NC
IND(4R)
INC(4R)
INB(2R)
INA(R)
INGND
REFGND
REF
ABSOLUTE MAXIMUM RATINGS
1
Analog Inputs
IND
2
, INC
2
, INB
2
. . . . . . . . . . . . . . . . . . . . –11 V to +30 V
INA, REF, INGND, REFGND
. . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to AVDD + 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to + 7 V
AVDD to DVDD,
AVDD to OVDD . . . . . . . . . . . . . . ±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to + 7 V
Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Internal Power Dissipation
3
. . . . . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation
4
. . . . . . . . . . . . . . . . . . . . . . 2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
See Analog Inputs section.
3
Specification is for device in free air: 48-Lead LQFP: q
JA
= 91°C/W, q
JC
= 30°C/W.
4
Specification is for device in free air: 48-Lead LFCSP: q
JC
= 26°C/W.
I
OH
500A
1.6mA I
OL
TO OUTPUT
PIN
1.4V
C
L
60pF
*
*
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing, SDOUT,
SYNC, SCLK Outputs, C
L
= 10 pF
t
DELAY
t
DELAY
0.8V
0.8V 0.8V
2V2V
2V
Figure 2. Voltage Reference Levels for Timing
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7665 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
C
The exposed paddle should be connected to GND.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

AD7665ASTZRL

Mfr. #:
Buy AD7665ASTZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16B 570kSPS Bipolar
Lifecycle:
New from this manufacturer.
Delivery:
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