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843004AGILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
DATA SHEET
FemtoClock® LVCMOS/Crystal-to-3.3V,
2.5V LVPECL Frequency Synthesizer
843004I
843004I Rev B 12/9/14 1 ©2014 Integrated Device Technology, Inc.
General Description
The 843004I is a 4 output LVPECL synthesizer optimized to generate
Fibre Channel reference clock frequencies. Using a 26.5625MHz
18pF parallel resonant crystal, the following frequencies can be
generated based on the two frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and
53.125MHz. The 843004I uses IDT’s 3
rd
generation low phase noise
VCO technology and can achieve 1ps or lower typical rms phase
jitter, easily meeting Fibre Channel jitter requirements. The 843004I
is packaged in a small 24-pin TSSOP package.
Features
• Four 3.3V differential LVPECL output pairs
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended clock input
• Supports the following output frequencies: 212.5MHz, 187.5MHz,
159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
• VCO range: 560MHz – 680MHz
• Output skew: 50ps (maximum)
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(2.55MHz – 20MHz): 0.47ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Bank A Frequency Table
Inputs
N Div. Value M/N Div. Value Output Frequency (MHz)Input Frequency (MHz) F_SEL1 F_SEL0 M Div. Value
26.5625 0 0 24 3 8 212.5
26.5625 0 1 24 4 6 159.375
26.5625 1 0 24 6 4 106.25
26.5625 1 1 24 12 2 53.125
26.04166 0 1 24 4 6 156.25
23.4375 0 0 24 3 8 187.5
Pin Assignment
843004I
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ1
Q1
V
CCO
Q0
nQ0
MR
nPLL_SEL
nc
V
CCA
F_SEL0
V
CC
F_SEL1
nQ2
Q2
Q3
V
CCO
VEE
nQ3
nc
nXTAL_SEL
TEST_CLK
V
EE
XTAL_IN
XTAL_OUT
11
0
1
0
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
M = 24 (fixed)
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
2
OSC
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
nPLL_SEL
nXTAL_SEL
XTAL_IN
XTAL_OUT
TEST_CLK
MR
F_SEL[1:0]
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
26.5625MHz
Block Diagram
Rev B 12/9/14 2 FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843004I DATA SHEET
Table 1. Pin Descriptions
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2
nQ1, Q1
Output Differential output pair. LVPECL interface levels.
3, 22 V
CCO
Power Output supply pins.
4, 5
Q0, nQ0
Output Differential output pair. LVPECL interface levels.
6 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
7 nPLL_SEL Input Pulldown
Selects between the PLL and TEST_CLK as input to the dividers. When LOW,
selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
8, 18
nc
Unused No connect.
9V
CCA
Power Analog supply pin.
10, 12
F_SEL0,
F_SEL1
Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
11 V
CC
Power Core supply pin.
13,
14
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
15, 19 V
EE
Power Negative supply pins.
16 TEST_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
17 nXTAL_SEL Input Pulldown
Selects between the single-ended TEST_CLK or crystal interface as the PLL
reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL.
LVCMOS/LVTTL interface levels.
20, 21
nQ3, Q3
Output Differential output pair. LVPECL interface levels.
23, 24
Q2, nQ2
Output Differential output pair. LVPECL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
R
PULLDOWN
Input Pulldown Resistor 51 k
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
3 Rev B 12/9/14
843004I DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, V
CC
= V
CCA
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Table 3B. Power Supply DC Characteristics, V
CC
= V
CCA
= V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Item Rating
Supply Voltage, V
CC
4.6V
Inputs, V
I
XTAL_IN
Other Inputs
0V to V
CC
-0.5V to V
CC
+ 0.5V
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance,
JA
70C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Core Supply Voltage 3.135 3.3 3.465 V
V
CCA
Analog Supply Voltage 3.135 3.3 3.465 V
V
CCO
Output Supply Voltage 3.135 3.3 3.465 V
I
EE
Power Supply Current 130 mA
I
CCA
Analog Supply Current Included in I
EE
15 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Core Supply Voltage 2.375 2.5 2.625 V
V
CCA
Analog Supply Voltage 2.375 2.5 2.625 V
V
CCO
Output Supply Voltage 2.375 2.5 2.625 V
I
EE
Power Supply Current 120 mA
I
CCA
Analog Supply Current Included in I
EE
12 mA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

843004AGILF

Mfr. #:
Buy 843004AGILF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 4 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
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