FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
13 Rev B 12/9/14
843004I DATA SHEET
Layout Guideline
Figure 6 shows a schematic example of the 843004I. An example of
LVEPCL termination is shown in this schematic. Additional LVPECL
termination approaches are shown in the LVPECL Termination
Application Note. In this example, an 18pF parallel resonant
26.5625MHz crystal is used. The C1= 27pF and C2 = 33pF are
recommended for frequency accuracy. For different board layout, the
C1 and C2 may be slightly adjusted for optimizing frequency
accuracy.
Figure 6. 843004I Schematic Example
VCC=3.3V
C3
10uF
+
-
VCCO=3.3V
R3
133
To Logic
Input
pins
3. 3V
VC C
Zo = 50 Ohm
Set Logic
Input to
'0'
C7
0. 1u
3. 3V
RD2
1K
VCC
VD D
VCC
R10
82.5
R4
82.5
VC CA
Logic Control Input Examples
VD D
C2
33pF
C4
0.01u
+
-
Zo = 50 Ohm
RD1
Not Install
Zo = 50 Ohm
RU2
Not Install
R7
133
R8
82.5
C9
0.1u
C1
27pF
Set Logic
Input to
'1'
R9
133
X1
26. 5625MH z
R2
10
To Logic
Input
pins
Zo = 50 Ohm
VC CO
R6
82.5
C6
0.1u
U1
ICS843004
1
2
3
4
5
6
7
8
9
10
11
1213
14
15
16
17
18
19
20
21
22
23
24
nQ1
Q1
VC CO
Q0
nQ0
MR
nPLL_SEL
NC
VCCA
F_SEL0
VCC
F_SEL1XTAL_OUT
XTAL_IN
VEE
TEST_CLK
nXTAL_SEL
VCC
VEE
nQ3
Q3
VC CO
Q2
nQ2
C8
0.1u
R5
133
RU1
1K
VC CO
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
14 Rev B 12/9/14
843004I DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 843004I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843004I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 130mA = 450.45mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_
MAX
(3.465V, with all outputs switching) = 450.45mW + 120mW = 570.45mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a moderate air
flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.571W * 65°C/W = 122.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance
JA
for 24 Lead TSSOP, Forced Convection
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 65°C/W 62°C/W
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
15 Rev B 12/9/14
843004I DATA SHEET
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 7.
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
V
CCO
– 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
– 0.9V
(V
CCO_MAX
– V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
COO_MAX
1.7V
(V
CCO_MAX
– V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
– 2V))/R
L
] * (V
CCO_MAX
– V
OH_MAX
) = [(2V – (V
CCO_MAX
– V
OH_MAX
))/R
L
] * (V
CCO_MAX
– V
OH_MAX
) =
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
– 2V))/R
L
] * (V
CCO_MAX
– V
OL_MAX
) = [(2V – (V
CCO_MAX
– V
OL_MAX
))/R
L
] * (V
CCO_MAX
– V
OL_MAX
) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
V
OUT
V
CCO
V
CCO
- 2V
Q1
RL
50Ω

843004AGILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 4 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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