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TDA7567PDTR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
I
2
C bus TDA7567PD
22/30 Doc ID 16903 Rev 2
8.2.4 Acknowledge
The transmitter puts a resistive high level on the SDA line during the acknowledge clock
pulse (see Figure 18). The receiver the acknowledges has to pull-down (low) the SDA line
during the acknowledge clock pulse, so that the SDA line is stable low during this clock
pulse.
Transmitter:
● master (µP) when it writes an address to the TDA7567PD
● slave (TDA7567PD) when the µP reads a data byte from TDA7567PD
Receiver:
● slave (TDA7567PD) when the µP writes an address to the TDA7567PD
● master (µP) when it reads a data byte from TDA7567PD
Figure 16. Data validity on the I
2
C bus
Figure 17. Timing diagram on the I
2
C bus
Figure 18. Acknowledge on the I
2
C bus
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
SCL
SDA
START
I
2
CBUS
STOP
D99AU1032
SCL
1
MSB
23789
SDA
START
ACKNOWLEDGMENT
FROM RECEIVER
D99AU1033
TDA7567PD Software specifications
Doc ID 16903 Rev 2 23/30
9 Software specifications
All the functions of the TDA7567PD are activated by I
2
C interface.
The bit 0 of the "Address Byte" defines if the next bytes are write instruction (from µP to
TDA7567PD) or read instruction (from TDA7567PD to µP).
Chip address
X = 0 Write to device
X = 1 Read from device
If R/W = 0, the µP sends 2 "Instruction Bytes": IB1 and IB2.
D7 D0
110110
(1)
1. Address selector bit, please refer to address selection description on Chapter 7.
XD8 Hex
Table 6. IB1
Bit Instruction decoding bit
D7 0
D6
Diagnostic enable (D6 = 1)
Diagnostic defeat (D6 = 0)
D5
Offset detection enable (D5 = 1)
Offset detection defeat (D5 = 0)
D4
Front channel
Gain = 26 dB (D4 = 0)
Gain = 16 dB (D4 = 1)
D3
Rear channel
Gain = 26dB (D3 = 0)
Gain = 16dB (D3 = 1)
D2
Mute front channels (D2 = 0)
Unmute front channels (D2 = 1)
D1
Mute rear channels (D1 = 0)
Unmute rear channels (D1 = 1)
D0
CD 2% (D0 = 0)
CD 10% (D0 = 1)
Table 7. IB2
Bit Instruction decoding bit
D7
Current detection threshold
High th (D7 = 0)
Low th (D7 =1)
D6 0
Software specifications TDA7567PD
24/30 Doc ID 16903 Rev 2
If R/W = 1, the TDA7567PD sends 4 "Diagnostics Bytes" to µP: DB1, DB2, DB3 and DB4.
D5
Normal muting time (D5 = 0)
Fast muting time (D5 = 1)
D4
Standby on - Amplifier not working - (D4 = 0)
Standby off - Amplifier working - (D4 = 1)
D3
Power amplifier mode diagnostic (D3 = 0)
Line driver mode diagnostic (D3 = 1)
D2
Current detection diagnostic enabled (D2 =1)
Current detection diagnostic defeat (D2 =0)
D1
Right channel power amplifier working in standard mode (D1 = 0)
Power amplifier working in high efficiency mode (D1 = 1)
D0
Left channel power amplifier working in standard mode (D0 = 0)
Power amplifier working in high efficiency mode (D0 = 1)
Table 7. IB2 (continued)
Bit Instruction decoding bit
Table 8. DB1
Bit Instruction decoding bit
D7 Thermal warning 1 active (D7 = 1) T = 140 °C
D6
Diag. cycle not activated or not terminated (D6 = 0)
Diag. cycle terminated (D6 = 1)
D5
Channel CH3
current detection IB2 (D7) = 0
Output peak current < 300 mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0)
Channel CH3
current detection IB2 (D7) = 1
Output peak current < 125 mA - Open load (D5 = 1)
Output peak current > 250 mA - Normal load (D5 = 0)
D4
Channel CH3
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
D3
Channel CH3
Normal load (D3 = 0)
Short load (D3 = 1)
D2
Channel CH3
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Offset diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
D1
Channel CH3
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
D0
Channel CH3
No short to GND (D1 = 0)
Short to GND (D1 = 1)
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TDA7567PDTR

Mfr. #:
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Manufacturer:
STMicroelectronics
Description:
Audio Amplifiers 4 x 50W Multi Quad Built-in Diagnostic
Lifecycle:
New from this manufacturer.
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