13
FN8194.3
October 12, 2006
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
Circuit #3 SPICE Macro Model
AC TIMING (over recommended operating conditions)
I
nput pulse levels V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times 10ns
Input and output timing level V
CC
x 0.5
5V
1533
100pF
SDA Output
10pF
R
H
R
TOTAL
C
H
25pF
C
W
C
L
10pF
R
W
R
L
Symbol Parameter Min. Max. Unit
f
SCL
Clock frequency 400 kHz
t
CYC
Clock cycle time 2500 ns
t
HIGH
Clock high time 600 ns
t
LOW
Clock low time 1300 ns
t
SU:STA
Start setup time 600 ns
t
HD:STA
Start hold time 600 ns
t
SU:STO
Stop setup time 600 ns
t
SU:DAT
SDA data input setup time 100 ns
t
HD:DAT
SDA data input hold time 30 ns
t
R
SCL and SDA rise time 300 ns
t
F
SCL and SDA fall time 300 ns
t
AA
SCL low to SDA data output valid time 900 ns
t
DH
SDA data output hold time 50 ns
T
I
Noise suppression time constant at SCL and SDA inputs 50 ns
t
BUF
Bus free time (prior to any transmission) 1300 ns
t
SU:WPA
WP, A0, A1, A2 and A3 setup time 0 ns
t
HD:WPA
WP, A0, A1, A2 and A3 hold time 0 ns
X9418
