7
FN8194.3
October 12, 2006
Figure 6. Increment/Decrement Timing Limits
Figure 7. Acknowledge Response from Receiver
SCL
SDA
V
W
/R
W
INC/DEC
CMD
Issued
Voltage Out
t
WRID
SCL from
Data Output
from Transmitter
1
89
START
Acknowledge
Master
Data Output
from Receiver
X9418
8
FN8194.3
October 12, 2006
Figure 8. Detailed Potentiometer Block Diagram
DETAILED OPERATION
Both XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
has a Wiper Counter Register and four Data
Registers. A detailed discussion of the register
organization and array operation follows.
Wiper Counter Register
The X9418 contains two wiper counter registers, one
for each XDCP potentiometer. The Wiper Counter
Register can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select
one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon power-up.
The WCR is a volatile register; that is, its contents are
lost when the X9418 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be
different from the value present at power-down.
Data Registers
Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
Register Descriptions
Data Registers, (6-Bit), Nonvolatile
Four 6-bit Data Registers for each XDCP. (eight 6-bit
registers in total).
{D5~D0}: These bits are for general purpose not
volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the Wiper Counter
Register on power-up.
Serial Data Path
From Interface
Circuitry
Register 0 Register 1
Register 2 Register 3
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
INC/DEC
Logic
UP/DN
CLK
Modified SCL
UP/DN
V
H
/R
H
V
L
/R
L
V
W
/R
W
If WCR = 00[H] then V
W
/R
W
= V
L
/R
L
If WCR = 3F[H] then V
W
/R
W
= V
H
/R
H
8 6
C
o
u
n
t
e
r
D
e
c
o
d
e
(WCR)
D5 D4 D3 D2 D1 D0
NV NV NV NV NV NV
(MSB) (LSB)
X9418
9
FN8194.3
October 12, 2006
Wiper Counter Register, (6-Bit), Volatile One 6-bit wiper counter register for each XDCP. (Four
6-bit registers in total.)
{D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.
Instruction Format
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
XFR Data Register (DR) to Wiper Counter Register (WCR)
WP5 WP4 WP3 WP2 WP1 WP0
VVVVVV
(MSB) (LSB)
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
WCR
addresses
S
A
C
K
wiper position
(sent by slave on SDA)
M
A
C
K
S
T
O
P
0101
A
3
A
2
A
1
A
0
1001000
P
0
00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
WCR
addresses
S
A
C
K
wiper position
(sent by master on SDA)
S
A
C
K
S
T
O
P
0101
A
3
A
2
A
1
A
0
1010000
P
0
00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
DR and WCR
addresses
S
A
C
K
wiper position/data
(sent by slave on SDA)
M
A
C
K
S
T
O
P
0101
A
3
A
2
A
1
A
0
1011
R
1
R
0
0
P
0
00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
DR and WCR
addresses
S
A
C
K
wiper position/data
(sent by master on SDA)
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101
A
3
A
2
A
1
A
0
1100
R
1
R
0
0P0 00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
DR and WCR
addresses
S
A
C
K
S
T
O
P
0101
A
3
A
2
A
1
A
0
1101
R
1
R
0
0
P
0
X9418

X9418WV24I-2.7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC XDCP DUAL 64-TAP 10K 24-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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