4
FN8194.3
October 12, 2006
The X9418 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9418 will respond with a final acknowledge.
Array Description
The X9418 is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
/R
W
) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9418
this is fixed as 0101[B].
Figure 1. Slave Address
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A
0
- A
3
inputs. The X9418 compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9418 to respond with an acknowledge. The
A
0
- A
3
inputs can be actively driven by CMOS input
signals or tied to V
CC
or V
SS
.
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9418
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9418 is still busy with the write operation no ACK will
be returned. If the X9418 has completed the write
operation an ACK will be returned, and the master can
then proceed with the next operation.
Flow 1. ACK Polling Sequence
Instruction Structure
The next byte sent to the X9418 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the two pots and when applicable they
point to one of four associated registers. The format is
shown Figure 2.
100
A3 A2 A1 A0
Device Type
Identifier
Device Address
1
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Further
Operation?
Issue
Instruction
Issue STOP
NO
YES
YES
Proceed
Issue STOP
NO
Proceed
X9418
5
FN8194.3
October 12, 2006
Figure 2. Instruction Byte Format
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued. The last bits (P0) select
which one of the two potentiometers is to be affected
by the instruction. Bit 1 is defined to be 0.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the wiper counter register and
one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed t
WRL
. A transfer from the wiper
counter register (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
WR
to complete. The transfer can occur
between one of the two potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between both of the
potentiometers and one of their associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9418; either between the host and
one of the Data Registers or directly between the host
and the wiper counter register. These instructions are:
Read Wiper Counter Register (read the current wiper
position of the selected pot), write Wiper Counter
Register (change current wiper position of the selected
pot), read Data Register (read the contents of the
selected nonvolatile register) and write Data Register
(write a new value to the selected Data Register). The
sequence of operations is shown in Figure 4.
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9418 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t
HIGH
) while SDA is HIGH, the selected wiper will
move one resistor segment towards the V
H
/R
H
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V
L
/R
L
terminal. A detailed
illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
Figure 3. Two-Byte Instruction Sequence
I1I2I3 I0 R1 R0 0 P0
Wiper Counter
Register Select
Register
Select
Instructions
S
T
A
R
T
0101A3A2A1A0A
C
K
I3 I2 I1 I0 R1 R0 0 P0 A
C
K
SCL
SDA
S
T
O
P
X9418
6
FN8194.3
October 12, 2006
Table 1. Instruction Set
Note: (7) 1/0 = data is one or zero
Figure 4. Three-Byte Instruction Sequence
Figure 5. Increment/Decrement Instruction Sequence
Instruction
Instruction Set
OperationI
3
I
2
I
1
I
0
R
1
R
0
P
1
P
0
Read Wiper Counter
Register
1 0 0 1 0 0 0 1/0 Read the contents of the Wiper Counter Register
pointed to by P
0
Write Wiper Counter
Register
1 0 1 0 0 0 0 1/0 Write new value to the Wiper Counter Register
pointed to by P
0
Read Data Register 1 0 1 1 1/0 1/0 0 1/0 Read the contents of the Data Register pointed to by
P
0
and R
1
- R
0
Write Data Register 1 1 0 0 1/0 1/0 0 1/0 Write new value to the Data Register pointed to by
P
0
and R
1
- R
0
XFR Data Register to
Wiper Counter Register
1 1 0 1 1/0 1/0 0 1/0 Transfer the contents of the Data Register pointed to
by P
0
and R
1
- R
0
to its associated Wiper Counter
Register
XFR Wiper Counter
Register to Data Register
1 1 1 0 1/0 1/0 0 1/0 Transfer the contents of the Wiper Counter Register
pointed to by P
0
to the Data Register pointed to by
R
1
- R
0
Global XFR Data
Registers to Wiper
Counter Registers
0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed
to by R
1
- R
0
of both pots to their respective Wiper
Counter Registers
Global XFR Wiper Count-
er Registers to Data Reg-
ister
1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter
Registers to their respective data Registers pointed
to by R
1
- R
0
of both pots
Increment/Decrement
Wiper Counter Register
0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Wiper Counter
Register pointed to by P
0
S
T
A
R
T
0 1 0 1 A3 A2 A1 A0 A
C
K
I3 I2 I1 I0 R1 R0 0 P0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
0 0 D5 D4 D3 D2 D1 D0
S
T
A
R
T
0 1 0 1 A3 A2 A1 A0 A
C
K
I3 I2 I1 I0 R0 0 P0 A
C
K
SCL
SDA
S
T
O
P
XX
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
R1
X9418

X9418WV24I-2.7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC XDCP DUAL 64-TAP 10K 24-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union