ADG733BRUZ-REEL7

REV. B
–4–
ADG733/ADG734–SPECIFICATIONS
1
DUAL SUPPLY
B Version
–40C
Parameter +25C to +85C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
SS
to V
DD
V
On Resistance (R
ON
) 2.5 typ V
S
= V
SS
to V
DD
, I
DS
= 10 mA;
4.5 5.0 max Test Circuit 1
On Resistance Match between 0.1 typ V
S
= V
SS
to V
DD
, I
DS
= 10 mA
Channels (R
ON
) 0.4 max
On Resistance Flatness (R
FLAT(ON)
) 0.5 typ V
S
= V
SS
to V
DD
, I
DS
= 10 mA
1.2 max
LEAKAGE CURRENTS V
DD
= +2.75 V, V
SS
= –2.75 V
Source OFF Leakage I
S
(OFF) ± 0.01 nA typ
V
S
= +2.25 V/–1.25 V, V
D
= –1.25 V/+2.25 V;
± 0.1 ± 0.3 nA max Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON) ± 0.01 nA typ
V
S
= V
D
= +2.25 V/–1.25 V, Test Circuit 3
± 0.1 ± 0.5 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
1.7 V min
Input Low Voltage, V
INL
0.7 V max
Input Current
I
INL
or I
INH
0.005 µA typ V
IN
= V
INL
or V
INH
± 0.1 µA max
C
IN
, Digital Input Capacitance 4 pF typ
DYNAMIC CHARACTERISTICS
2
t
ON
21 ns typ R
L
= 300 , C
L
= 35 pF;
35 ns max V
S
= 1.5 V, Test Circuit 4
t
OFF
10 ns typ R
L
= 300 , C
L
= 35 pF;
16 ns max V
S
= 1.5 V, Test Circuit 4
ADG733 t
ON
(EN)21 ns typ R
L
= 300 , C
L
= 35 pF;
40 ns max V
S
= 1.5 V, Test Circuit 5
t
OFF
(EN)10 ns typ R
L
= 300 , C
L
= 35 pF;
16 ns max V
S
= 1.5 V, Test Circuit 5
Break-Before-Make Time Delay, t
D
13 ns typ R
L
= 300 , C
L
= 35 pF;
1 ns min V
S
= 1.5 V, Test Circuit 6
Charge Injection ± 5pC typ V
S
= 0 V, R
S
= 0 , C
L
= 1 nF;
Test Circuit 7
Off Isolation –72 dB typ R
L
= 50 , C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
Channel-to-Channel Crosstalk –67 dB typ R
L
= 50 , C
L
= 5 pF, f = 1 MHz;
Test Circuit 9
–3 dB Bandwidth 200 MHz typ R
L
= 50 , C
L
= 5 pF, Test Circuit 10
C
S
(OFF) 11 pF typ f = 1 MHz
C
D
, C
S
(ON) 34 pF typ f = 1 MHz
POWER REQUIREMENTS V
DD
= 2.75 V
I
DD
0.001 µA typ Digital Inputs = 0 V or 2.75 V
1.0 µA max
I
SS
0.001 µA typ V
SS
= –2.75 V
1.0 µA max Digital Inputs = 0 V or 2.75 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(V
DD
= +2.5 V 10%, V
SS
= –2.5 V 10%, GND = 0 V, unless otherwise noted.)
REV. B
ADG733/ADG734
–5–
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V
Analog Inputs
2
. . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V or
30 mA, Whichever Occurs First
Digital Inputs
2
. . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
16-Lead TSSOP, θ
JA
Thermal Impedance . . . . . . . 150.4°C/W
20-Lead TSSOP, θ
JA
Thermal Impedance . . . . . . . . . 143°C/W
16-Lead QSOP, θ
JA
Thermal Impedance . . . . . . . 149.97°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at A, EN, IN, S, or D will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
PIN CONFIGURATIONS
10
9
13
12
11
15
14
16
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
ADG733
S2B
S1B
D1
D2
V
DD
S2A
S3B
D3
A1
A0
S1A
S3A
EN
V
SS
GND
A2
14
13
12
11
17
16
15
19
18
20
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
ADG734
NC = NO CONNECT
IN1
S4B
D4
S4A
IN4
S1A
D1
S1B
S3B
NC
V
DD
V
SS
GND
S2B
D2
S2A
IN2
IN3
S3A
D3
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG733/ADG734 feature proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
TSSOP/QSOP TSSOP
REV. B
ADG733/ADG734
–6–
Table I. ADG733 Truth Table
A2 A1 A0 EN ON Switch
XXX1 None
0000D1-S1A, D2-S2A, D3-S3A
0010D1-S1B, D2-S2A, D3-S3A
0100D1-S1A, D2-S2B, D3-S3A
0110D1-S1B, D2-S2B, D3-S3A
1000D1-S1A, D2-S2A, D3-S3B
1010D1-S1B, D2-S2A, D3-S3B
1100D1-S1A, D2-S2B, D3-S3B
1110D1-S1B, D2-S2B, D3-S3B
X = Don’t Care.
Table II. ADG734 Truth Table
Logic Switch A Switch B
0 OFF ON
1ONOFF
TERMINOLOGY
V
DD
Most Positive Power Supply Potential
V
SS
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to
ground close to the device.
I
DD
Positive Supply Current
I
SS
Negative Supply Current
GND Ground (0 V) Reference
S Source Terminal. May be an input or output.
DDrain Terminal. May be an input or output.
A
X
Logic Control Input
EN Active low device enable
V
D
(V
S
)Analog Voltage on Terminals D and S
R
ON
Ohmic Resistance between D and S
R
ON
On Resistance Match between any Two Channels (i.e., R
ON
max and R
ON
min)
R
FLAT(ON)
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over
the specified analog signal range.
I
S
(OFF) Source Leakage Current with the Switch “OFF”
I
D
, I
S
(ON) Channel Leakage Current with the Switch “ON”
V
INL
Maximum Input Voltage for Logic “0”
V
INH
Minimum Input Voltage for Logic “1”
I
INL
(I
INH
) Input Current of the Digital Input
C
S
(OFF) “OFF” Switch Source Capacitance. Measured with reference to ground.
C
D
, C
S
(ON) “ON” Switch Capacitance. Measured with reference to ground.
C
IN
Digital Input Capacitance
t
ON
Delay Time Measured between the 50% and 90% Points of the Digital Inputs and the Switch “ON” Condition
t
OFF
Delay Time Measured between the 50% and 90% Points of the Digital Input and the Switch “OFF” Condition
t
ON
(EN)Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “ON” Condition
t
OFF
(EN)Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “OFF” Condition
t
OPEN
“OFF” Time Measured between the 80% Points of Both Switches when Switching from One Address State to
Another
Charge A Measure of the Glitch Impulse Transferred Injection from the Digital Input to the Analog Output during Switching
Off Isolation A Measure of Unwanted Signal Coupling through an “OFF” Switch.
Crosstalk A Measure of Unwanted Signal that Is Coupled through from One Channel to Another as a Result of Para-
sitic Capacitance
On Response The Frequency Response of the “ON” Switch
Insertion Loss The Loss Due to the On Resistance of the switch

ADG733BRUZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs 72dB 2.5 Ohm 160MHz CMOS Triple SPDT
Lifecycle:
New from this manufacturer.
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