Operation modes M48T08, M48T08Y, M48T18
10/31 Doc ID 2411 Rev 11
Table 3. READ mode AC characteristics
Note: Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V
(except where noted).
2.2 WRITE mode
The M48T08/18/08Y is in the WRITE mode whenever W, E1, and E2 are active. The start of
a WRITE is referenced from the latter occurring falling edge of W
or E1, or the rising edge of
E2. A WRITE is terminated by the earlier rising edge of W
or E1, or the falling edge of E2.
The addresses must be held valid throughout the cycle. E1
or W must return high or E2 low
for a minimum of t
E1HAX
or t
E2LAX
from chip enable or t
WHAX
from WRITE enable prior to the
initiation of another READ or WRITE cycle. Data-in must be valid t
DVWH
prior to the end of
WRITE and remain valid for t
WHDX
afterward. G should be kept high during WRITE cycles to
avoid bus contention; however, if the output bus has been activated by a low on E1
and G
and a high on E2, a low on W
will disable the outputs t
WLQZ
after W falls.
Symbol Parameter
(1)
M48T08/M48T18/T08Y
Unit–100/–10 (T08Y) –150/–15 (T08Y)
Min Max Min Max
t
AVAV
READ cycle time 100 150 ns
t
AVQV
Address valid to output valid 100 150 ns
t
E1LQV
Chip enable 1 low to output valid 100 150 ns
t
E2HQV
Chip enable 2 high to output valid 100 150 ns
t
GLQV
Output enable low to output valid 50 75 ns
t
E1LQX
Chip enable 1 low to output transition 10 10 ns
t
E2HQX
Chip enable 2 high to output transition 10 10 ns
t
GLQX
Output enable low to output transition 5 5 ns
t
E1HQZ
Chip enable 1 high to output Hi-Z 50 75 ns
t
E2LQZ
Chip enable 2 low to output Hi-Z 50 75 ns
t
GHQZ
Output enable high to output Hi-Z 40 60 ns
t
AXQX
Address transition to output transition 5 5 ns
