Operation modes M48T08, M48T08Y, M48T18
8/31 Doc ID 2411 Rev 11
2 Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock
oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 1FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T08/18/08Y
includes a clock control circuit which updates the clock bytes with current information once
per second. The information can be accessed by the user in the same manner as any other
location in the static memory array.
The M48T08/18/08Y also has its own power-fail detect circuit. The control circuitry
constantly monitors the single 5 V supply for an out-of-tolerance condition. When V
CC
is out
of tolerance, the circuit write protects the SRAM, providing a high degree of data security in
the midst of unpredictable system operation brought on by low V
CC
. As V
CC
falls below the
battery backup switchover voltage (V
SO
), the control circuitry connects the battery which
maintains data and clock operation until valid power returns.
Table 2. Operating modes
Note: X = V
IH
or V
IL
;
V
SO
= Battery backup switchover voltage.
Mode V
CC
E1 E2 G W DQ0-DQ7 Power
Deselect
4.75 to 5.5 V
or
4.5 to 5.5 V
V
IH
X X X High Z Standby
Deselect X V
IL
X X High Z Standby
WRITE V
IL
V
IH
XV
IL
D
IN
Active
READ V
IL
V
IH
V
IL
V
IH
D
OUT
Active
READ V
IL
V
IH
V
IH
V
IH
High Z Active
Deselect
V
SO
to
V
PFD
(min)
(1)
1. See Table 11 on page 22 for details.
XXXXHigh ZCMOS standby
Deselect ≤ V
SO
(1)
X X X X High Z Battery backup mode
