M48T08, M48T08Y, M48T18 Operation modes
Doc ID 2411 Rev 11 13/31
2.3 Data retention mode
With valid V
CC
applied, the M48T08/18/08Y operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
CC
falls within the V
PFD
(max), V
PFD
(min) window. All outputs
become high impedance, and all inputs are treated as “Don't care.
Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
PFD
(min), the
user can be assured the memory will be in a write protected state, provided the V
CC
fall time
is not less than t
F
. The M48T08/18/08Y may respond to transient noise spikes on V
CC
that
reach into the deselect window during the time the device is sampling V
CC
. Therefore,
decoupling of the power supply lines is recommended.
When V
CC
drops below V
SO
, the control circuit switches power to the internal battery which
preserves data and powers the clock. The internal button cell will maintain data in the
M48T08/18/08Y for an accumulated period of at least 10 years when V
CC
is less than V
SO
.
Note: Requires use of M4T32-BR12SH SNAPHAT
®
top when using the SOH28 package.
As system power returns and V
CC
rises above V
SO
, the battery is disconnected and the
power supply is switched to external V
CC
.
Write protection continues until V
CC
reaches V
PFD
(min) plus t
rec
(min). E1 should be kept
high or E2 low as V
CC
rises past V
PFD
(min) to prevent inadvertent WRITE cycles prior to
system stabilization. Normal RAM operation can resume t
rec
after V
CC
exceeds V
PFD
(max).
For more information on battery storage life refer to the application note AN1012.
2.4 Power-fail interrupt pin
The M48T08/18/08Y continuously monitors V
CC
. When V
CC
falls to the power-fail detect trip
point, an interrupt is immediately generated. An internal clock provides a delay of between
10 µs and 40 µs before automatically deselecting the M48T08/18/08Y. The INT
pin is an
open drain output and requires an external pull-up resistor, even if the interrupt output
function is not being used.
Clock operations M48T08, M48T08Y, M48T18
14/31 Doc ID 2411 Rev 11
3 Clock operations
3.1 Reading the clock
Updates to the TIMEKEEPER
®
registers should be halted before clock data is read to
prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are
only data registers and not the actual clock counters, so updating the registers can be halted
without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, the seventh bit in the control
register. As long as a '1' remains in that position, updating is halted. After a halt is issued,
the registers reflect the count; that is, the day, date, and the time that were current at the
moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a '0.'
3.2 Setting the clock
The eighth bit of the control register is the WRITE bit. Setting the WRITE bit to a '1,' like the
READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with
the correct day, date, and time data in 24-hour BCD format (on Tabl e 5). Resetting the
WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual
TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits
marked as '0' in Ta bl e 5 must be written to '0' to allow for normal TIMEKEEPER and RAM
operation.
See the application note AN923, “TIMEKEEPER
®
rolling Into the 21
st
century” for
information on century rollover.
M48T08, M48T08Y, M48T18 Clock operations
Doc ID 2411 Rev 11 15/31
Keys:
S = SIGN bit
FT = FREQUENCY TEST bit (set to '0' for normal clock operation)
R = READ bit
W = WRITE bit
ST = STOP bit
0 = Must be set to '0'
3.3 Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit (ST) is the MSB of the seconds register. Setting it to a '1' stops the
oscillator. The M48T08/18/08Y (in the PCDIP28 package) is shipped from
STMicroelectronics with the STOP bit set to a '1.' When reset to a '0,' the M48T08/18/08Y
oscillator starts within one second.
Note: To guarantee oscillator startup after initial power-up, first write the STOP bit (ST) to '1,' then
reset to '0.'
3.4 Calibrating the clock
The M48T08/18/08Y is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. A typical M48T08/18/08Y is accurate within 1 minute per month at 25 °C without
calibration. The devices are tested not to exceed ± 35 ppm (parts per million) oscillator
frequency error at 25 °C, which equates to about ±1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M48T08/18/08Y improves to better than
+1/–2 ppm at 25 °C.
The oscillation rate of any crystal changes with temperature. Figure 8 on page 17 shows the
frequency error that can be expected at various temperatures. Most clock chips compensate
for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The
Table 5. Register map
Address
Data
Function/range
BCD format
D7 D6 D5 D4 D3 D2 D1 D0
1FFFh 10 years Year Year 00-99
1FFEh 0 0 0 10 M Month Month 01-12
1FFDh 0 0 10 date Date Date 01-31
1FFCh 0 FT 0 0 0 Day Day 01-07
1FFBh 0 0 10 hours Hours Hours 00-23
1FFAh 0 10 minutes Minutes Minutes 00-59
1FF9h ST 10 seconds Seconds Seconds 00-59
1FF8h W R S Calibration Control

M48T18-100PC1

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Real Time Clock 64K (8Kx8) 100ns
Lifecycle:
New from this manufacturer.
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