Rev. Initiator Issue Date Description Page #
A RDW 8/13/2012
1. Removed "Differential" from DS title and Recommended Application, corrected typo's in
Description.
2. Corrected spelling error in pullup/pulldown text under pinout
3. Updated all electrical tables and added "Industry Limit" column to "Phase Jitter
Parameters".
4. Updated Byte3[0] to be consistent with Byte 2. Updated Byte6[7:6] definition.
5. Added thermal data to page 12.
6. Added NLG32 to "Package Outline and Package Dimensions" on page 13.
7. Move to final
1,2,5-
8,10,
12,13
B RDW 2/28/2013
1. "Input/Supply/Common Parameters" table modified as follows:
a. Updated Single-ended input logic thresholds to include missing mid-level on tri-level inputs. Adjusted logic
thresholds as follows:
i. Changed VIH min. from 0.65*VDD to 0.75*VDD
ii. Changed VIL max. from 0.35*VDD to 0.25*VDD
iii. Added missing mid-level input voltage spec (VIM) of 0.4*VDD to 0.6*VDD.
iv. Clarified conditions for these specifications, accordingly.
b. Clarified the operating conditions and voltages of the SMBus to make it clear that the SMBus operates at
<3.3V by addition of footnotes 4 and 5 to "Input/Supply/Common Parameters" table.
2. Slight modifications of Slew Rates and typical values in the "DIF 0.7V Low Power Differential Outputs" table.
3. "Current Consumption" table modifed as follows:
a. Overall current consumption values lowered
b. VDDA is now grouped with VDD1.8 instead of VDDR
c. Added separate current specs for PLL bypass mode.
d. Clarified that CKPWRDG_PD# is low for power down current.
4. "Output Duty Cycle, Jitter, Skew and PLL Characterisitics" table modifed as follows:
a. Bypass mode Input-to-Output skew changed from 3000 to 4500ps to 2550 to 4200ps. Typical value
reduced from 3500ps to 3370ps.
b. Separate Output-to-Output skew spec added for Industrial temp.
c. Additive cycle-to-cycle jitter spec reduced to 1ps max.
5. "Phase Jitter Parameters" modifed as follows:
a. Corrected typo in PLL Mode conditions for tjPHSGMII. Frequency integration range is 1.5MHz to 10MHz.
Bypass mode conditions were correct.
5-8
C RDW 11/26/2014
1. Updated front page text for consistency and updated block diagram resistor colors to
highlight internal resistors.
2. Updated max frequency of 100MHz PLL mode from 110MHz to 140MHz
3. Updated max frequency of 125MHz PLL mode from 137.5MHz to 175MHz
4. Updated max frequency of 50MHz PLL mode from 55MHz to 65MHz
5. Updated Key Specifications with addtive phase jitter.
6. Added additive phase jitter plot to specifications.
Various
D RDW 4/3/2015
1. Updated block diagram with new format showing individual outputs instead of bussed
outputs.
2. Updated pin out and pin descriptions to show ePad on package connected to ground.
1-4
E RDW 4/22/2016
1. Updated max frequency of 100MHz PLL mode to 140MHz
2. Updated max frequency of 125MHz PLL mode to 175MHz
3. Updated max frequency of 50MHz PLL mode to 65MHz
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