4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 8 REVISION E 04/28/16
9DBV0431 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
Electrical Characteristics–Phase Jitter Parameters
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
-3dB point in High BW Mode 2 2.7 4 MHz 1,5
-3dB point in Low BW Mode 1 1.4 2 MHz 1,5
PLL Jitter Peaking t
JPEAK
Peak Pass band Gain 1.2 2 dB 1
Duty Cycle t
DC
Measured differentially, PLL Mode 45 50.1 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode @100MHz -1 -0.1 1 % 1,3
t
dBYP
= 50% 2550 3370 4200 ps 1
t
dPLL
= 50% 0 112 200 ps 1,4
Commercial Operating Range, V
= 50% 33 50 ps 1,4
Industrial Operating Range, V
= 50% 33 55 ps 1,4
PLL mode 13 50 ps 1,2
Additive Jitter in Bypass Mode 0.1 1 ps 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
3
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4
All outputs at default slew rate
5
The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
PLL Bandwidth BW
Skew, Input to Output
Skew, Output to Output t
sk3
Jitter, Cycle to cycle t
jcyc-cyc
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
INDUSTRY
LIMIT UNITS Notes
hPCIeG1
PCIe Gen 1 32 52 86 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.8 1.4 3
ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
2.4
2.6 3.1
ps
(rms)
1,2
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.5
0.6 1
ps
(rms)
1,2,4
t
jphSGMII
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
1.9 2.2 3
ps
(rms)
1,6
t
jphPCIeG1
PCIe Gen 1 0.1 5.0 N/A ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.2 0.3 N/A
ps
(rms)
1,2,4
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(rms)
1,2,4
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
(rms)
1,2,4
t
jphSGMIIM0
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
165 200 N/A
fs
(rms)
1,6
t
jphSGMIIM1
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
251 300 N/A
fs
(rms)
1,6
1
Guaranteed by design and characterization, not 100% tested in production.
4
For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5
Driven by 9FGV0831 or equivalent
6
Driven by Rohde&Schwarz SMA100
Additive Phase Jitter,
Bypass Mode
t
jphPCIeG2
2
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
Phase Jitter, PLL Mode
t
jphPCIeG2
