OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

9DBV0431AKILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 4 REVISION E 04/28/16
9DBV0431 DATASHEET
Test Loads
Driving LVDS
Rs
Rs
Low-Power Differential Output Test Load
2pF 2pF
5 inches
Zo=100ohm
Alternate Differential Output Terminations
Rs Zo Units
33 100
27 85
Ohms
LVDS CLK
Input
L4
R8b
R7b
R8a
R7a
3.3 Volts
Cc
Cc
Rs
Rs
Driving LVDS
Driving LVDS inputs with the 9DBV0431
Receiver has
termination
Receiver does not
have termination
R7a, R7b 10K ohm 140 ohm
R8a, R8b 5.6K ohm 75 ohm
Cc 0.1 uF 0.1 uF
Vcm 1.2 volts 1.2 volts
Component
Value
Note
REVISION E 04/28/16 5 4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)
9DBV0431 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0431. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Electrical Characteristics–Clock Input Parameters
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
Power supply voltage VDDxx Applies to all VDD pins -0.5 2.5 V 1,2
Input Voltage V
IN
-0.5 V
DD
+0.5V V 1, 3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.6V V 1
Storage Temperature Ts -65 150 °C 1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage - DIF_IN V
IHDI F
Differential inputs
(single-ended measurement)
600 800 1150 mV 1
Input Low Voltage - DIF_IN V
ILDIF
Differential inputs
(single-ended measurement)
V
SS
- 300 0 300 mV 1
Input Common Mode Voltage
- DIF_IN
V
COM
Common Mode Input Voltage 300 725 mV 1
Input Amplitude - DIF_IN V
SWING
Peak to Peak value (VIHDIF - VILDIF), single-ended 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA 1
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle J
DIFI n
Differential Measurement 0 150 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through +/-75mV window centered around differential zero
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 6 REVISION E 04/28/16
9DBV0431 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
1.8V Supply Voltage VDD
Supply voltage for core, analog and LVCMOS
outputs
1.7 1.8 1.9 V 1
T
COM
Commmercial range 0 25 70 °C 1
T
IND
Industrial range -40 25 85 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus 0.75 V
DD
V
DD
+ 0.3 V 1
Input Mid Voltage V
IM
Single-ended tri-level inputs ('_tri' suffix) 0.4 V
DD
0.6 V
DD
V1
Input Low Voltage V
IL
Single-ended inputs, except SMBus -0.3 0.25 V
DD
V1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
F
ib
yp
Bypass mode 1 200 MHz 2
F
i
p
ll100
100MHz PLL mode 50 100 140 MHz 2
F
i
p
ll125
125MHz PLL mode 62.5 125 175 MHz 2
F
i
p
ll62
50MHz PLL mode 25 50 65 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,6
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.6 1 ms 1,2
Input SS Modulation
Frequency
f
MODIN
Allowable Frequency
(Triangular Modulation)
30 31.5 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 clocks 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
175 300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 1,2
Trise t
R
Rise time of single-ended control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V, see note 4 for V
DDSMB
< 3.3V 0.8 V 1,4
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V, see note 5 for V
DDSMB
< 3.3V 2.1 3.6 V 1,5
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
1.7 3.6 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating Frequency
f
MAXSMB
Maximum SMBus operating frequency 400 kHz 1,7
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
Ambient Operating
Temperature
Input Current
Input Frequency
Capacitance
3
Time from deassertion until outputs are >200 mV
6
DIF_IN input
7
The differential input clock must be running for the SMBus to be active
4
For V
DDSMB
< 3.3V, V
ILSMB
<= 0.25V
DDSMB
5
For V
DDSMB
< 3.3V, V
IHSMB
>= 0.7V
DDSMB
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

9DBV0431AKILFT

Mfr. #:
Buy 9DBV0431AKILFT
Manufacturer:
IDT
Description:
Clock Buffer 4 O/P 1.8V PCIE BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet