UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 18 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
A dedicated V1 supply comparator (V1 Monitor) monitors V1 for undervoltage events
(V
O(V1)
< V
UV(VFI)
). This allows the application to receive a supply warning interrupt if one
of the lower V1 undervoltage reset thresholds has been selected (see Table 13
).
Regulator V1 is overload protected. The maximum output current available at pin V1
depends on the voltage applied at pin BAT14 (see Section 9 “
Static characteristics”). Total
power dissipation should be taken into account for thermal reasons.
6.6.3.2 Voltage regulator V2
Voltage regulator V2 provides a 5 V supply for the CAN transmitter. An external buffer
capacitor should be connected to pin V2.
V2 is controlled autonomously by the CAN transceiver control system and is activated on
any detected CAN-bus activity, or if the CAN transceiver is enabled by the application
microcontroller. V2 is short-circuit protected and will be disabled in an overload situation.
Dedicated bits in the System Diagnosis register and the Interrupt register provide V2
status feedback to the application.
In addition to being controlled autonomously by the CAN transceiver control system, V2
can be activated manually via bit V2C (in Table 12
). This allows V2 to be used in
applications when CAN is not actively used (e.g. while CAN is off-line). In general, V2
should not be used with other application hardware while CAN is in use.
If regulator V2 is unable to start up within the V2 clamped LOW time (> t
V2(CLT)
), or if a
short circuit is detected while V2 is active, V2 is disabled and bit V2D in the Diagnosis
register is cleared (see Table 8
). In addition, bit CTC in the Physical Layer register is set
and the V2C bit is cleared (see in Table 12
).
Any of the following events will reactivate regulator V2:
• Clearing bit CTC while CAN is in Active mode
• Wake up via CAN while CAN is not in Active mode
• Setting bit V2C
• Entering CAN Active mode
6.6.4 Switched battery output V3
V3 is a high-side switched BAT42-related output which is used to drive external loads
such as wake-up switches or relays. The features of V3 are as follows:
• Three application controlled modes of operation; ON, OFF and Cyclic mode.
• Two different cyclic modes allow for the supply of external wake-up switches; these
switches are powered intermittently, thus reducing system power consumption when a
switch is continuously active; the wake-up input of the SBC is synchronized with the
V3 cycle time.
• The switch is protected against current overloads. If V3 is overloaded, pin V3 is
automatically disabled. The corresponding Diagnosis register bit (V3D) is reset and a
VFI interrupt is generated (if enabled). During Sleep mode, a wake-up is forced and
the corresponding reset source code (0100) can be read via the RSS bits of the
System Status register. This signals that the wake-up source via V3 supplied wake-up
switches has been lost.
