UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 32 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
[1] V2D will be set when V2 is reactivated after a failure. See Section 6.6.3.2.
6.12.6 Interrupt Enable register and Interrupt Enable Feedback register
These registers allow the SBC interrupt enable bits to be set, cleared and read back.
1 and 0 CANMD [1:0] CAN Mode Diagnosis 11 CAN is in Active mode
10 CAN is in On-line mode
01 CAN is in On-line Listen mode
00 CAN is in Off-line mode, or V2 is not active
Table 8. System Diagnosis register bit description
…continued
Bit Symbol Description Value Function
Table 9. Interrupt Enable and Interrupt Enable Feedback register bit description
Bit Symbol Description Value Function
15 and 14 A1, A0 register address 01 select the Interrupt Enable register
13 RRS Read Register Select 1 read the Interrupt register
0 read the Interrupt Enable Feedback register
12 RO Read Only 1 read the register selected by RRS without writing to
Interrupt Enable register
0 read the register selected by RRS and write to Interrupt
Enable register
11 WTIE Watchdog Time-out
Interrupt Enable
[1]
1 a watchdog overflow during Standby mode causes an
interrupt instead of a reset event (interrupt based cyclic
wake-up feature)
0 no interrupt forced on watchdog overflow; a reset is forced
instead
10 OTIE OverTemperature
Interrupt Enable
1 exceeding or dropping below the temperature warning limit
causes an interrupt
0 no interrupt forced
9 GSIE Ground Shift Interrupt
Enable
1 exceeding or dropping below the GND shift limit causes an
interrupt
0 no interrupt forced
8 SPIFIE SPI clock count Failure
Interrupt Enable
1 wrong number of CLK cycles (more than, or less than 16)
forces an interrupt; from Start-up mode and Restart mode a
reset is performed instead of an interrupt
0 no interrupt forced; SPI access is ignored if the number of
cycles does not equal 16
7 BATFIE BAT Failure Interrupt
Enable
1 falling edge at SENSE forces an interrupt
0 no interrupt forced
6 VFIE Voltage Failure Interrupt
Enable
1 clearing of V1D, V2D or V3D forces an interrupt
0 no interrupt forced
5 CANFIE CAN Failure Interrupt
Enable
1 any change of the CAN Failure status bits forces an
interrupt
0 no interrupt forced
4 - reserved 0 reserved for SBCs with LIN transceiver