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UJA1066TW/5V0/T,51

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 25 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
6.12 SPI interface
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave and multi-master operation. The SPI is configured
for full duplex data transfer, so status information is returned when new control data is
shifted in. The interface also offers a read-only access option, allowing registers to be
read back by the application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
• SCS - SPI chip select; active LOW
• SCK - SPI clock; default level is LOW due to low-power concept
• SDI - SPI data input
• SDO - SPI data output; floating when pin SCS is HIGH
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock
edge; see Figure 12
.
Fig 12. SPI timing protocol
SCS
SCK
01
sampled
floating floating
mce63
4
X
X
MSB 14 13 12 01 LSB
MSB 14 13 12 01 LSB
X
SDI
SDO
02 03 04 15 16
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 26 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
To protect against wrong or illegal SPI instructions, the SBC detects the following SPI
failures:
• SPI clock count failure (wrong number of clock cycles during one SPI access): only
16 clock periods are allowed during an SCS cycle. Any deviation from the 16 clock
cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC.
In Start-up and Restart modes, a reset is forced instead of an interrupt.
• Forbidden mode changes according to Figure 3 result in an immediate system reset
• Illegal Mode register code. Undefined operating mode or watchdog period coding
results in an immediate system reset; see Section 6.12.3
.
6.12.1 SPI register mapping
Any control bit that can be set by software can be read by the application. This facilitates
software debugging and allows control algorithms to be implemented.
Watchdog serving and mode setting are performed within the same access cycle; this
allows an SBC mode change to occur only while serving the watchdog.
Each register contains 12 data bits; the other 4 bits are used for register selection and
read/write definition.
6.12.2 Register overview
The SPI interface provides access to all SBC registers; see Table 4. The first two bits (A1
and A0) of the message header define the register address. The third bit is the read
register select bit (RRS) used to select one of two feedback registers. The fourth bit (RO)
allows ‘read-only’ access to one of the feedback registers. Which of the SBC registers can
be accessed also depends on the SBC operating mode.
Table 4. Register overview
Register
address bits
(A1, A0)
Operating
mode
Write access (RO = 0) Read access (RO = 0 or RO = 1)
Read Register Select
(RRS) bit = 0
Read Register Select
(RRS) bit = 1
00 all modes Mode register System Status register System Diagnosis register
01 Normal mode;
Standby mode;
Flash mode
Interrupt Enable register Interrupt Enable Feedback
register
Interrupt register
Start-up mode;
Restart mode
Special Mode register Interrupt Enable Feedback
register
Special Mode Feedback
register
10 Normal mode;
Standby mode
System Configuration
register
System Configuration
Feedback register
General Purpose Feedback
register 0
Start-up mode;
Restart mode;
Flash mode
General Purpose register 0 System Configuration
Feedback register
General Purpose Feedback
register 0
11 Normal mode;
Standby mode
Physical Layer Control
register
Physical Layer Control
Feedback register
General Purpose Feedback
register 1
Start-up mode;
Restart mode;
Flash mode
General Purpose register 1 Physical Layer Control
Feedback register
General Purpose Feedback
register 1
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 27 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
6.12.3 Mode register
The Mode register is used to define and re-trigger the watchdog and to select the SBC
operating mode. The Mode register also contains the global enable output bit (EN) and
the Software Development Mode (SDM) control bit. Cyclic access to the Mode register is
required during system operation to serve the watchdog. This register can be written to in
all modes.
At system start-up, the Mode register must be written to within t
WD(init)
of pin RSTN being
released (HIGH-level on pin RSTN). Any write access is checked for proper watchdog and
system mode coding. If an illegal code is detected, access is ignored by the SBC and a
system reset is forced in accordance with the state diagram of the system controller; see
Figure 3
.
[1] Flash mode can be entered only with the watchdog service sequence ‘Normal mode to Flash mode to Normal mode to Flash mode’,
while observing the watchdog trigger rules. With the last command of this sequence the SBC forces a system reset, and enters Start-up
mode to prepare the microcontroller for flash memory download. The four RSS bits in the System Status register reflect the reset source
information, confirming the Flash entry sequence. By using the Initializing Flash mode (within t
WD(init)
after system reset) the SBC will
now successfully enter Flash mode.
[2] See Section 6.13.1
.
Table 5. Mode register bit description (bits 15 to 12 and 5 to 0)
Bit Symbol Description Value Function
15 and 14 A1, A0 register address 00 select Mode register
13 RRS Read Register
Select
1 read System Diagnosis register
0 read System Status register
12 RO Read Only 1 read selected register without writing to Mode register
0 read selected register and write to Mode register
11 to 6 NWP[5:0] see Table 6
5 to 3 OM[2:0] Operating Mode 001 Normal mode
010 Standby mode
011 initialize Flash mode
[1]
100 Sleep mode
101 initialize Normal mode
110 leave Flash mode
111 Flash mode
[1]
2 SDM Software
Development
Mode
1 Software development mode enabled
[2]
0 normal watchdog, interrupt, reset monitoring and fail-safe
behavior
1 EN Enable 1 EN output pin HIGH
0 EN output pin LOW
0 - reserved 0 reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70

UJA1066TW/5V0/T,51

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Buy UJA1066TW/5V0/T,51
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC IC CAN/LIN FAIL-SAFE HS 32
Lifecycle:
New from this manufacturer.
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