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CS8406-DSZR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
22 DS580F6
CS8406
8.7 Interrupt 1 Status (07h) (Read Only)
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ me ans the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets all bits to ‘0’, unless the Interrupt Mode is set to level and
the interrupt source is still true. Status bits that are masked off in the associated mask register will always
be ‘0’ in this register. This register defaults to 00h.
TSLIP - AES3 transmitter source data slip interrupt
In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this bit
will go high every time a data sample is dropped or repeated. When TCBL is an input, this bit will go high
on receipt of a new TCBL signal.
EFTC - E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer in
the C bit buffer management process.
8.8 Interrupt 2 Status (08h) (Read Only)
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ me ans the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets all bits to ‘0’, unless the Interrupt Mode is set to level and
the interrupt source is still true. Status bits that are masked off in the associated mask register will always
be ‘0’ in this register. This register defaults to 00h.
EFTU - E to F U-buffer transfer interrupt. (Block Mode only) The source of this bit is true during the E to F
buffer transfer in the U bit buffer management process.
8.9 Interrupt 1 Mask (09h)
The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is un-
masked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0,
the error is mas ked, meaning that its occurrence will not affect the INT pin or the status register. The bit
positions align with the corresponding bits in Interrupt 1 register. This register defaults to 00h.
7 6 543210
TSLIP 0 0 0 0 0 EFTC 0
7 6 543210
00000EFTU00
7 6 543210
TSLIPM 0 0 0 0 0 EFTCM 0
DS580F6 23
CS8406
8.10 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh)
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three
ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode,
the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT
pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin be-
comes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends
on the INT[1:0] bits. These registers default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
8.11 Interrupt 2 Mask (0Ch)
The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is un-
masked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0,
the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit
positions align with the corresponding bits in Interrupt 2 register. This register defaults to 00h.
8.12 Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three
ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode,
the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT
pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin be-
comes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends
on the INT[1:0] bits. These registers default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
8.13 Channel Status Data Buffer Control (12h)
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
Default = ‘0’
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
76543210
TSLIP1 0 0 0 0 0 EFTC1 0
TSLIP0 0 0 0 0 0 EFTC0 0
76543210
00000EFTUM00
76543210
00000EFTU100
00000EFTU000
76543210
0 0 BSEL 0 0 EFTCI CAM 0
24 DS580F6
CS8406
Note: There are separate complete buffers for the Channel Status and User bits. This control bit deter-
mines which buffer appears in the address space.
EFTCI - E to F C-data buffer transfer inhibit bit.
Default = ‘0’
0 - Allow C-data E to F buffer transfers
1 - Inhibit C-data E to F buffer transfers
CAM - C-data buffer control port access mode bit
Default = ‘0’
0 - One-Byte Mode
1 - Two-Byte Mode
8.14 User Data Buffer Control (13h)
UD - User bit data source specifier
Default = ‘0’
0 - U Pin is the source of transmitted U data
1 - U data buffer is the source of transmitted U data
UBM1:0 - Sets the operating mode of the AES3 User bit manager
Default = ‘00’
00 - Transmit all zeros mode
01 - Block Mode
10 - Reserved
11 - Reserved
EFTUI - E to F U-data buffer transfer inhibit bit (valid in Block Mode only).
Default = ‘0’
0 - Allow U-data E to F buffer transfers
1 - Inhibit U-data E to F buffer transfers
8.15 Channel Status Bit or User Bit Data Buffer (20h - 37h)
Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to
Block Mode) is accessible through these register addresses.
8.16 CS8406 I.D. and Version Register (7Fh) (Read Only)
ID[3:0] - ID code for the CS8406. Permanently set to 1110
VER[3:0] = 0001 (revision A)
VER[3:0] = 0010 (revision B)
7 6 543210
0 0 0 UD UBM1 UBM0 0 EFTUI
7 6 543210
ID3 ID2 ID1 ID0 VER3 VER2 VER1 VER0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

CS8406-DSZR

Mfr. #:
Buy CS8406-DSZR
Manufacturer:
Cirrus Logic
Description:
Audio Transmitters, Receivers, Transceivers IC 192 kHz Digital Audio Transmitter
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