1. General description
The NVT2008/NVT2010 are bidirectional voltage level translators operational from 1.0 V
to 3.6 V (V
ref(A)
) and 1.8 V to 5.5 V (V
ref(B)
), which allow bidirectional voltage translations
between 1.0 V and 5 V without the need for a direction pin in open-drain or push-pull
applications. Bit widths of 8-bit to 10-bit are offered for level translation application with
transmission speeds < 33 MHz for an open-drain system with a 50 pF capacitance and a
pull-up of 197 .
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (R
on
) of the
switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the
drain pull-up supply voltage (V
pu(D)
) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control.
When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,
respectively, allowing bidirectional data flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by V
ref(B)
. To ensure the high-impedance state during
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
Provides bidirectional voltage translation with no direction pin
Less than 1.5 ns maximum propagation delay
Allows voltage level translation between:
1.0 V V
ref(A)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
ref(B)
1.2 V V
ref(A)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
ref(B)
1.8 V V
ref(A)
and 3.3 V or 5 V V
ref(B)
2.5 V V
ref(A)
and 5 V V
ref(B)
3.3 V V
ref(A)
and 5 V V
ref(B)
NVT2008; NVT2010
Bidirectional voltage-level translator for open-drain and
push-pull applications
Rev. 3 — 27 January 2014 Product data sheet
NVT2008_NVT2010 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 27 January 2014 2 of 33
NXP Semiconductors
NVT2008; NVT2010
Bidirectional voltage-level translator
Low 3.5 ON-state connection between input and output ports provides less signal
distortion
5 V tolerant I/O ports to support mixed-mode signal operation
High-impedance An and Bn pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 4 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Packages offered: TSSOP20, DHVQFN20, TSSOP24, DHVQFN24, HVQFN24
3. Ordering information
[1] GTL2003 = NVT2008.
[2] GTL2010 = NVT2010.
3.1 Ordering options
Table 1. Ordering information
Type number Topside
mark
Number
of bits
Package
Name Description Version
NVT2008BQ
[1]
NVT2008 8 DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
SOT764-1
NVT2008PW
[1]
NVT2008 8 TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
NVT2010BQ
[2]
NVT2010 10 DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5 5.5 0.85 mm
SOT815-1
NVT2010BS
[2]
N010 10 HVQFN24 plastic thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 4 4 0.85 mm
SOT616-1
NVT2010PW
[2]
NVT2010 10 TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
Table 2. Ordering options
Type number Orderable
part number
Package Packing method Minimum
order quantity
Temperature
NVT2008BQ NVT2008BQ,115 DHVQFN20 Reel 7” Q1/T1
*Standard mark SMD
3000 T
amb
= 40 C to +85 C
NVT2008PW NVT2008PW,118 TSSOP20 Reel 13” Q1/T1
*Standard mark SMD
2500 T
amb
= 40 C to +85 C
NVT2010BQ NVT2010BQ,118 DHVQFN24 Reel 13” Q1/T1
*Standard mark SMD
3000 T
amb
= 40 C to +85 C
NVT2010BS NVT2010BS,115 HVQFN24 Reel 7” Q1/T1
*Standard mark SMD
1500 T
amb
= 40 C to +85 C
NVT2010BS,118 HVQFN24 Reel 13” Q1/T1
*Standard mark SMD
6000 T
amb
= 40 C to +85 C
NVT2010PW NVT2010PW,118 TSSOP24 Reel 13” Q1/T1
*Standard mark SMD
2500 T
amb
= 40 C to +85 C
NVT2008_NVT2010 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 27 January 2014 3 of 33
NXP Semiconductors
NVT2008; NVT2010
Bidirectional voltage-level translator
4. Functional diagram
5. Pinning information
5.1 Pinning
5.1.1 8-bit in TSSOP20 and DHVQFN20 packages
Fig 1. Logic diagram of NVT2008/10 (positive logic)
002aae132
A1
An
VREFA
GND
VREFB
B1
Bn
EN
SW
SW
NVT20xx
Fig 2. Pin configuration for TSSOP20 Fig 3. Pin configuration for DHVQFN20
NVT2008PW
GND EN
VREFA VREFB
A1 B1
A2 B2
A3 B3
A4 B4
A5 B5
A6 B6
A7 B7
A8 B8
002aae225
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
002aae226
NVT2008BQ
Transparent top view
B7
A6
A7
B6
A5 B5
A4 B4
A3 B3
A2 B2
A1 B1
VREFA VREFB
A8
B8
GND
EN
9
12
8 13
7 14
6 15
5 16
4 17
3 18
2 19
10
11
1
20
terminal 1
index area

NVT2008BQ,115

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Translation - Voltage Levels +/-50mA 1.5ns 1-5.5V
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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