NVT2008_NVT2010 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 27 January 2014 4 of 33
NXP Semiconductors
NVT2008; NVT2010
Bidirectional voltage-level translator
5.1.2 10-bit in TSSOP24, DHVQFN24 and HVQFN24 packages
Fig 4. Pin configuration for TSSOP24 Fig 5. Pin configuration for DHVQFN24
Fig 6. Pin configuration for HVQFN24
NVT2010PW
GND EN
VREFA VREFB
A1 B1
A2 B2
A3 B3
A4 B4
A5 B5
A6 B6
A7 B7
A8 B8
A9 B9
A10 B10
002aae227
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
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NVT2010BQ
Transparent top view
B9
A8
A9
B8
A7 B7
A6 B6
A5 B5
A4 B4
A3 B3
A2 B2
A1 B1
VREFA VREFB
A10
B10
GND
EN
11 14
10 15
9 16
8 17
7 18
6 19
5 20
4 21
3 22
2 23
12
13
1
24
terminal 1
index area
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NVT2010BS
Transparent top view
B7
A6
A7
B6
A5 B5
A4 B4
A3 B3
A2 B2
A8
A9
A10
B10
B9
B8
A1
VREFA
GND
EN
VREFB
B1
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7
8
9
10
11
12
24
23
22
21
20
19
NVT2008_NVT2010 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 27 January 2014 5 of 33
NXP Semiconductors
NVT2008; NVT2010
Bidirectional voltage-level translator
5.2 Pin description
[1] 8-bit NVT2008 available in TSSOP20, DHVQFN20 packages.
[2] 10-bit NVT2010 available in TSSOP24, DHVQFN24, HVQFN24 packages.
Table 3. Pin description
Symbol Pin Description
NVT2008BQ,
NVT2008PW
[1]
NVT2010BQ,
NVT2010PW
[2]
NVT2010BS
[2]
GND 1 1 22 ground (0 V)
VREFA 2 2 23 low-voltage side reference supply
voltage for An
A1 3 3 24 low-voltage side; connect to
VREFA through a pull-up resistor
A2441
A3552
A4663
A5774
A6885
A7996
A8 10 10 7
A9 - 11 8
A10 - 12 9
B1 18 22 19 high-voltage side; connect to
VREFB through a pull-up resistor
B2 17 21 18
B3 16 20 17
B4 15 19 16
B5 14 18 15
B6 13 17 14
B7 12 16 13
B8 11 15 12
B9 - 14 11
B10 - 13 10
VREFB 19 23 20 high-voltage side reference
supply voltage for Bn
EN 20 24 21 switch enable input; connect to
VREFB and pull-up through a
high resistor
NVT2008_NVT2010 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 27 January 2014 6 of 33
NXP Semiconductors
NVT2008; NVT2010
Bidirectional voltage-level translator
6. Functional description
Refer to Figure 1 “Logic diagram of NVT2008/10 (positive logic).
6.1 Function table
[1] EN is controlled by the V
ref(B)
logic levels and should be at least 1 V higher than V
ref(A)
for best translator
operation.
7. Application design-in information
The NVT2008/10 can be used in level translation applications for interfacing devices or
systems operating at different interface voltages with one another. The NVT2008/10 is
ideal for use in applications where an open-drain driver is connected to the data I/Os. The
NVT2008/10 can also be used in applications where a push-pull driver is connected to the
data I/Os.
7.1 Enable and disable
The NVT20xx has an EN input that is used to disable the device by setting EN LOW,
which places all I/Os in the high-impedance state.
Table 4. Function selection (example)
H = HIGH level; L = LOW level.
Input EN
[1]
Function
HAn=Bn
L disconnect
(1) The applied voltages at V
ref(A)
and V
pu(D)
should be such that V
ref(B)
is at least 1 V higher than
V
ref(A)
for best translator operation.
Fig 7. Typical application circuit (switch always enabled)
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A1
A2
VREFA
GND
3
4
VREFB
1
6
5
B1
B2
8EN
SW
SW
NVT2002
7
200 kΩ
R
PU
R
PU
V
pu(D)
= 3.3 V
(1)
I
2
C-BUS
DEVICE
SCL
SDA
V
CC
GND
2
V
ref(A)
= 1.8 V
(1)
R
PU
R
PU
I
2
C-BUS
MASTER
SCL
SDA
V
CC
GND

NVT2008BQ,115

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Translation - Voltage Levels +/-50mA 1.5ns 1-5.5V
Lifecycle:
New from this manufacturer.
Delivery:
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