72831L10PFG Datasheet 72831L10PFG, 72841L10PFG, 72801L10PFG | P1-P3

IDT, IDT logo and the SyncFIFO logo are registered trademarks of Integrated Device Technology, Inc.

MARCH 2013

DUAL CMOS SyncFIFO™

DUAL 256 x 9, DUAL 512 x 9,

DUAL 1,024 x 9, DUAL 2,048 x 9,

DUAL 4,096 x 9, DUAL 8,192 x 9

IDT72801

IDT72811

IDT72821

IDT72831

IDT72841

IDT72851

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

FEATURES:

••

•

The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs

••

•

The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs

••

•

The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs

••

•

The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs

••

•

The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs

••

•

The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs

••

• Offers optimal combination of large capacity, high speed,

design flexibility and small footprint

••

• Ideal for prioritization, bidirectional, and width expansion

applications

••

• 10 ns read/write cycle time for the IDT72801/72811/72821/72831/

72841/72851

••

• Separate control lines and data lines for each FIFO

••

• Separate Empty, Full, Programmable Almost-Empty and Almost-

Full flags for each FIFO

••

• Enable puts output data lines in high-impedance state

••

• Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin

Quad Flatpack (STQFP)

•

Industrial temperature range (–40

°°

C to +85

°°

C) is available

••

• Green parts available, see ordering information

DESCRIPTION:

The IDT72801/72811/72821/72831/72841/72851 are dual synchronous

(clocked) FIFOs. The device is functionally equivalent to two IDT72201/72211/

72221/72231/72241/72251 FIFOs in a single package with all associated

control, data, and flag lines assigned to separate pins.

Each of the two FIFOs (designated FIFO A and FIFO B) contained in the

IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port (DA0

- DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each

input port is controlled by a free-running clock (WCLKA, WCLKB), and two Write

Enable pins (WENA1, WENA2, WENB1, WENB2). Data is written into each of

the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)

when the appropriate write enable pins are asserted.

The output port of each FIFO bank is controlled by its associated clock pin

(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,

RENB2). The Read Clock can be tied to the Write Clock for single clock operation

or the two clocks can run asynchronous of one another for dual clock operation.

An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO

for three-state output control.

Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA,

FFB). Two programmable flags, Almost-Empty (PAEA, PAEB) and Almost-Full

(PAFA, PAFB), are provided for each FIFO bank to improve memory utilization.

If not programmed, the programmable flags default to empty+7 for PAEA and

PAEB, and full-7 for PAFA and PAFB.

The IDT72801/72811/72821/72831/72841/72851 architecture lends itself

to many flexible configurations such as:

• 2-level priority data buffering

• Bidirectional operation

• Width expansion

• Depth expansion

These FIFOs is fabricated using high-performance submicron CMOS

technology.

FUNCTIONAL BLOCK DIAGRAM

WCLKA

WENA1

WENA2

DA0 - DA8

LDA

OFFSET REGISTER

INPUT REGISTER

RAM ARRAY

256 x 9, 512 x 9,

1024 x 9, 2048 x 9,

4096 x 9, 8192 x 9

WRITE CONTROL

LOGIC

WRITE POINTER

RESET LOGIC

OUTPUT REGISTER

OEA

RSA

QA0 - QA8

RCLKA

RENA1

RENA2

READ CONTROL

LOGIC

READ POINTER

FLAG

LOGIC

EFA

PAEA

PAFA

FFA

3034 drw 01

WCLKB

WENB1

WENB2

DB0 - DB8

LDB

OFFSET REGISTER

INPUT REGISTER

WRITE CONTROL

LOGIC

WRITE POINTER

RESET LOGIC

OUTPUT REGISTER

OEB

RSB

QB0 - QB8

RCLKB

RENB1

RENB2

READ CONTROL

LOGIC

READ POINTER

FLAG

LOGIC

EFB

PAEB

PAFB

FFB

RAM ARRAY

256 x 9, 512 x 9,

1024 x 9, 2048 x 9,

4096 x 9, 8192 x 9

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO

DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

MARCH 2013

QA1

QA2

QA3

QA4

QA5

QA6

QA7

QA8

VCC

WENA2/LDA

WCLKA

WENA1

RSA

DA7

DA6

QB0

FFB

EFB

OEB

RENB2

RCLKB

RENB1

GND

PAEB

PAFB

DB1

DB2

DB3

DB4

FFA

EFA

OEA

RENA2

RCLKA

RENA1

GND

QB7

QB6

QB5

QB4

QB3

QB2

QB1

DA5

DA4

DA3

DA2

DA1

DA0

PAFA

PAEA

WENB2/LDB

WCLKB

WENB1

RSB

DB7

DB6

DB5

3034 drw 02

PIN CONFIGURATION

TQFP (PN64-1, order code: PF)

STQFP (PP64-1, order code: TF)

TOP VIEW

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO

DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

MARCH 2013

Symbol Name I/O Description

DA0-DA8 A Data Inputs I 9-bit data inputs to RAM array A.

DB0-DB8 B Data Inputs I 9-bit data inputs to RAM array B.

RSA, RSB Reset I When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to

the first location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go

LOW. After power-up, a reset of both FIFOs A and B is required before an initial Write.

WCLKA Write Clock I Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write

WCLKB enable(s) are asserted.

WENA1 Write Enable 1 I If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only Write

WENB1 Enable pin that can be used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO

on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to have two write enables,

WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into the FIFO. Data

will not be written into the FIFO if FFA (FFB) is LOW.

WENA2/

LDA Write Enable 2/ I FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB)

WENB2/LDB Load is HIGH at reset, this pin operates as a second write enable. If WENA2/LDA

(WENB2/

LDB

) is LOW

at reset this pin operates as a control to load and read the programmable

flag offsets for its respective

array.

If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW

and WENA2 (WENB2) must be HIGH to write data into FIFO A (B). Data will not be written into FIFO A (B)

if FFA (FFB) is LOW. If the FIFO is configured to have programmable flags, LDA (LDB) is held LOW to write or

read the programmable flag offsets.

QA0-QA8 A Data Outputs O 9-bit data outputs from RAM array A.

QB0-QB8 B Data Outputs O 9-bit data outputs from RAM array B.

RCLKA Read Clock I Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1

RCLKB (RENB1) and RENA2 (RENB2) are asserted.

RENA1 Read Enable 1 I When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every

RENB1 LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.

RENA2 Read Enable 2 I When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every

RENB2 LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.

OEA Output Enable I When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the

OEB outputs DA0-DA8 (DB0-DB8) will be in a high-impedance state.

EFA Empty Flag O When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited.

EFB When EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).

PAEA Programmable O When PAEA (PAEB) is LOW, FIFO A (B) is almost-empty based on the offset programmed into the

PAEB Almost-Empty appropriate offset register. The default offset at reset is Empty+7. PAEA (PAEB) is synchronized to

Flag RCLKA (RCLKB).

PAFA Programmable O When PAFA (PAFB) is LOW, FIFO A (B) is almost-full based on the offset programmed into the appropriate

PAFB Almost-Full Flag offset register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB).

FFA Full Flag O When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited.

FFB When FFA (FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).

VCC Power +5V power supply pin.

GND Ground 0V ground pin.

PIN DESCRIPTIONS

The IDT72801/72811/72821/72831/72841/72851s two FIFOs, referred

to as FIFO A and FIFO B, are identical in every respect. The following

description defines the input and output signals for FIFO A. The correspond-

ing signal names for FIFO B are provided in parentheses.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

72831L10PFG

Mfr. #:

Buy 72831L10PFG

Manufacturer:

IDT

Description:

FIFO DUAL 2K X 9

Lifecycle:

New from this manufacturer.

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