8
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
TM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
NUMBER OF WORDS IN ARRAY A
FFAFFA
FFAFFA
FFA
PAFAPAFA
PAFAPAFA
PAFA
PAEAPAEA
PAEAPAEA
PAEA
EFAEFA
EFAEFA
EFA
NUMBER OF WORDS IN ARRAY B
FFBFFB
FFBFFB
FFB
PAFBPAFB
PAFBPAFB
PAFB
PAEBPAEB
PAEBPAEB
PAEB
EFBEFB
EFBEFB
EFB
72801 72811 72821
000HHLL
1 to n
(1)
1 to n
(1)
1 to n
(1)
HHLH
(n+1) to (256-(m+1)) (n+1) to (512-(m+1)) (n+1) to (1,024-(m+1)) H H H H
(256-m)
(2)
to 255 (512-m)
(2)
to 511 (1,024-m)
(2)
to 1,023 H L H H
256 512 1,024 L L H H
NUMBER OF WORDS IN ARRAY A
FFAFFA
FFAFFA
FFA
PAFAPAFA
PAFAPAFA
PAFA
PAEAPAEA
PAEAPAEA
PAEA
EFAEFA
EFAEFA
EFA
NUMBER OF WORDS IN ARRAY B
FFBFFB
FFBFFB
FFB
PAFBPAFB
PAFBPAFB
PAFB
PAEBPAEB
PAEBPAEB
PAEB
EFBEFB
EFBEFB
EFB
72831 72841 72851
00 0HHLL
1 to n
(1)
1 to n
(1)
1 to n
(1)
HHLH
(n+1) to (2,048-(m+1)) (n+1) to (4,096-(m+1)) (n+1) to (8,192-(m+1)) H H H H
(2,048-m)
(2)
to 2,047 (4,096-m)
(2)
to 4,095 (8,192-m)
(2)
to 8,191 H L H H
2,048 4,096 8,192 L L H H
Programmable Almost–Full Flag (PAFA, PAFB) — PAFA (PAFB) will
go LOW when the amount of data in Array A (B) reaches the almost-full condition.
If no reads are performed after Reset, PAFA ( PAFB) will go LOW after (256-m)
writes to the IDT72801's FIFO A (B); (512-m) writes to the IDT72811's FIFO
A (B); (1,024-m) writes to the IDT72821's FIFO A (B); (2,048-m) writes to the
IDT72831's FIFO A (B); (4,096-m) writes to the IDT72841's FIFO A (B); or
(8,192-m) writes to the IDT72851's FIFO A (B).
FFA ( FFB) is synchronized with respect to the LOW-to-HIGH transition of the
Write Clock WCLKA (WCLKB). The offset “m” is defined in the Full Offset
registers.
If there is no Full offset specified, PAFA ( PAFB) will go LOW at Full-7 words.
PAFA ( PAFB) is synchronized with respect to the LOW-to-HIGH transition
of WCLKA (WCLKB).
Programmable Almost–Empty Flag (PAEA, PAEB) —
PAEA ( PAEB) will
go LOW when the read pointer is "n+1" locations less than the write pointer. The
offset "n" is defined in the Empty Offset registers. If no reads are performed after
Reset, PAEA ( PAEB) will go HIGH after "n+1" writes to FIFO A (B).
If there is no Empty offset specified, PAEA ( PAEB) will go LOW at Empty+7
words.
PAEA ( PAEB) is synchronized with respect to the LOW-to-HIGH transition
of the Read Clock RCLKA (RCLKB).
Data Outputs (QA
0 – QA8, QB0 – QB8 ) — QA0 - QA8 are the nine data
outputs for memory array A, QB0 - QB8 are the nine data outputs for memory
array B.
TABLE 1: STATUS FLAGS FOR A AND B FIFOS
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
