SSM2804
Rev. 0 | Page 19 of 36
I
2
C SOFTWARE CONTROL INTERFACE
The I
2
C interface provides access to the user-selectable control
registers and operates with a 2-wire interface.
Each control register consists of 16 bits, MSB first. Bits[B15:B9]
are the register map address, and Bits[B8:B0] are the register data
for the associated register map.
SDA generates the serial control data-word, and SCL
clocks the serial data. The I
2
C bus address (Bits[A7:A1]) is
0x3B (01110110 for write and 01110111 for read). Bit A0 is
the designated read/write bit.
P
98
1TO 7
98
1TO 7
98
1TO 7
S
SDA
SCL
START ADDR R/W
ACK ACKSUBADDRESS ACK STOPDATA
09960-029
Figure 37. 2-Wire I
2
C Generalized Clocking Diagram
WRITE
SEQUENCE
READ
SEQUENCE
SA1A7 A0 A(S) A(S) SB15 B9 0
01
0P
0... A1A7 A0 A(S)... B0 B8B7 A(M) A(M)...
B0B7 P...
......
DEVICE
ADDRESS
DEVICE
ADDRESS
REGISTER
ADDRESS
SA1A7 A0 A(S) A(S) A(S)B15 B9 B8
0
... ...
DEVICE
ADDRESS
REGISTER
ADDRESS
REGISTER
DATA
(SLAVE DRIVE)
REGISTER
DATA
S/P = START/STOP BIT.
A0 = I
2
C R/W BIT.
A(S) = ACKNOWLEDGE BY SLAVE.
(M) = ACKNOWLEDGE BY MASTER.
(M) = ACKNOWLEDGE BY MASTER (INVERSION).
09960-030
Figure 38. I
2
C Write and Read Sequences
