SSM2804
Rev. 0 | Page 34 of 36
ADDITIONAL CONTROL, ADDRESS 0x0E
Table 43. Additional Control Register Bit Map
D7 D6 D5 D4 D3 D2 D1 D0
LIMLOCK HPLIM[2:0] LIM_MODE TO EDGE[1:0]
Table 44. Additional Control Register Bit Descriptions
Bit Name Description Settings
LIMLOCK
Headphone limiter lock bit. After the limiter is
locked, the locked levels cannot be reset until
the SSM2804 is powered down, the SD
pin is
strobed low, or all eight bits of the software
reset register (Register 0x10) are set to 0.
0 = disable (default)
1 = enable
HPLIM[2:0] Headphone limiter level adjust. 000 = off (default)
001 = ±1.13 V
010 = ±0.98 V
011 = ±0.80 V
100 = ±0.57 V
101 = ±0.40 V
110 = ±0.28 V
111 = ±0.22 V
LIM_MODE Headphone limiter mode selection.
0 = hardware mode (external resistor limiter via SD
pin; default)
1 = software mode (I
2
C adjustable limiter)
TO Timeout control. 0 = 30 ms (default)
1 = 60 ms
EDGE[1:0] Class-D output stage edge control. 00 = normal mode (default)
01 = slow edge
10 = slower edge (PVDD > 3.0 V recommended)
11 = slowest edge (PVDD > 4.0 V recommended)
