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AD7843ARQZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD7843
Rev. B | Page 15 of 20
POWER VS. THROUGHPUT RATE
By using the power-down options on the AD7843 when not
converting, the average power consumption of the device
decreases at lower throughput rates. Figure 23 shows how, as the
throughput rate is reduced while maintaining the DCLK
frequency at 2 MHz, the device remains in its power-down state
longer and the average current consumption over time drops
accordingly.
For example, if the AD7843 is operated in a 24 DCLK
continuous sampling mode, with a throughput rate of 10 kSPS
and a SCLK of 2 MHz, and the device is placed in the power-
down mode between conversions, (PD0, PD1 = 0, 0), the current
consumption is calculated as follows. The power dissipation
during normal operation is typically 210 µA (V
CC
= 2.7 V). The
power-up time of the ADC is instantaneous, so when the part is
converting, it consumes 210 µA. In this mode of operation, the
part powers up on the fourth falling edge of DCLK after the
start bit is recognized. It goes back into power-down at the end
of conversion on the 20th falling edge of DCLK. This means the
part consumes 210 µA for 16 DCLK cycles only, 8 µs, during
each conversion cycle. With a throughput rate of 10 kSPS, the
cycle time is 100 µs and the average power dissipated during
each cycle is (8/100) × (210 µA) = 16.8 µA.
SUPPLY CURRENT (µA)
1
100
10
1000
0 120
THROUGHPUT (kSPS)
02144-B-023
40 600 20 80 100
f
DCLK
= 16 × f
SAMPLE
f
DCLK
= 2MHz
V
CC
= 2.7V
T
A
= –40°C TO +95°C
Figure 23. Supply Current vs. Throughput (µA)
Table 7. Power Management Options
PD1 PD0
PENIRQ
Description
0 0 Enabled
This configuration results in power-down of the device between conversions. The AD7843 only powers down
between conversions. Once PD1 and PD0 are set to 0, 0, the conversion is performed first, and the AD7843
powers down upon completion of that conversion. At the start of the next conversion, the ADC instantly powers
up to full power. This means there is no need for additional delays to ensure full operation, and the very first
conversion is valid. The Y− switch is on while in power-down.
0 1 Disabled
This configuration results in the same behavior as when PD1 and PD0 have been programmed with 0, 0, except
that PENIRQ
is disabled. The Y− switch is off while in power-down.
1 0 Enabled
This configuration results in keeping the AD7843 permanently powered up with PENIRQ
enabled.
1 1 Disabled
This configuration results in keeping the AD7843 always powered up with PENIRQ
disabled.
AD7843
Rev. B | Page 16 of 20
SERIAL INTERFACE
Figure 24 shows the typical operation of the serial interface of
the AD7843. The serial clock provides the conversion clock and
also controls the transfer of information to and from the
AD7843. One complete conversion can be achieved with 24
DCLK cycles.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
takes the BUSY output and the serial bus
out of three-state. The first eight DCLK cycles are used to write
to the control register via the DIN pin. The control register is
updated in stages as each bit is clocked in. Once the converter
has enough information about the following conversion to set
the input multiplexer and switches appropriately, the converter
enters acquisition mode and, if required, the internal switches
are turned on. During the acquisition mode, the reference input
data is updated. After the three DCLK cycles of acquisition, the
control word is complete (the power management bits are now
updated) and the converter enters conversion mode. At this
point, track-and-hold goes into hold mode, the input signal is
sampled, and the BUSY output goes high (BUSY returns low on
the next falling edge of DCLK). The internal switches may also
turn off at this point if in single-ended mode.
The next 12 DCLK cycles are used to perform the conversion
and to clock out the conversion result. If the conversion is
ratiometric (SER/
DFR
set low), the internal switches are on
during the conversion. A 13th DCLK cycle is needed to allow
the DSP/microcontroller to clock in the LSB. Three more DCLK
cycles clock out the three trailing zeroes and complete the 24
DCLK transfer. The 24 DCLK cycles can be provided from a
DSP or via three bursts of 8 clock cycles from a microcontroller.
02144-B-024
CS
DCLK
DIN
BUSY
DOUT
X/Y SWITCHES
1
(SER/DFR HIGH)
X
/Y SWITCHES
1,2
(SER/DFR LOW)
THREE-STATE
(START)
IDLE
OFF OFF
(MSB) (LSB)
ON
ON
OFF OFF
ACQUIRE CONVERSION IDLE
ZERO FILLED
THREE-STATE
THREE-STATE
THREE-STATE
t
ACQ
18 8 8
11 10 9 8 7 6 5 4 3 2 1 0
11
S A2 PD1 PD0A1 A0
MODE
SER/
DFR
NOTES
1
Y DRIVERS ARE ON WHEN X+ IS SELECTED INPUT CHANNEL (A2–A0 = 001); X DRIVERS ARE ON WHEN Y+ IS SELECTED INPUT CHANNEL (A2–A0 = 101).
1
WHEN PD1, PD0 = 10 OR 00, Y– WILL TURN ON AT THE END OF THE CONVERSION.
2
DRIVERS WILL REMAIN ON IF POWER-DOWN MODE IS 11 (NO POWER-DOWN) UNTIL SELECTED INPUT CHANNEL, REFERENCE MODE,
1
OR POWER-DOWN MODE IS CHANGED.
Figure 24. Conversion Timing, 24 DCLKS per Conversion Cycle, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.
AD7843
Rev. B | Page 17 of 20
DETAILED SERIAL INTERFACE TIMING
Figure 25 shows the detailed timing diagram for serial
interfacing to the AD7843. Writing information to the control
register takes place on the first eight rising edges of DCLK in a
data transfer. The control register is written to only if a START
bit is detected (see the Control Register section) on DIN. The
initiation of the following conversion also depends on the
presence of the START bit. Throughout the eight DCLK cycles
when data is being written to the part, the DOUT line is driven
low. The MSB of the conversion result is clocked out on the
falling edge of the ninth DCLK cycle and is valid on the rising
edge of the tenth DCLK cycle; therefore, nine leading zeros can
be clocked out prior to the MSB. This means the data seen on
the DOUT line in the 24 DCLK conversion cycle is presented in
the form of nine leading zeros, twelve bits of data, and three
trailing zeros.
The rising edge of
CS
puts the bus and the BUSY output back
into three-state, the DIN line is ignored, and, if a conversion is
in progress at the time, this is also aborted. However, if
CS
is not
brought high after the completion of the conversion cycle, then
the part waits for the next START bit to initiate the next
conversion. This means that each conversion does not
necessarily need to be framed by
CS
, because once
CS
goes low,
the part detects each START bit and clocks in the control word
after it on DIN. When the AD7843 is in the 12-bit conversion
mode, a second START bit is not detected until seven DCLK
pulses have elapsed after a control word is clocked in on DIN,
that is, another START bit can be clocked in on the eighth
DCLK rising edge after a control word is written to the device
(see the Fifteen Clocks per Cycle section). If the device is in the
8-bit conversion mode, a second START bit is not recognized
until three DCLK pulses elapse after the control word is clocked
in, that is, another START bit can be clocked in on the fourth
DCLK rising edge after a control word is written to the device.
Because a START bit can be recognized during a conversion, the
control word for the next conversion can be clocked in during
the current conversion, enabling the AD7843 to complete a
conversion cycle in less than 24 DCLKs.
02144-B-025
CS
DCLK
DIN
BUSY
DOUT
DB11
PD0
DB10
t
1
t
4
t
5
t
6
t
6
t
9
t
10
t
11
t
7
t
2
t
3
t
8
t
12
Figure 25. Detailed Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7843ARQZ-REEL7

Mfr. #:
Buy AD7843ARQZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Touch Screen Controllers IC 27V 12-BIT TouchScrn Digitizer
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