MAX8792
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
26 ______________________________________________________________________________________
A reasonable minimum value for h is 1.5, but adjusting this
up or down allows trade-offs between V
SAG
, output capac-
itance, and minimum operating voltage. For a given value
of h, the minimum operating voltage can be calculated as:
where V
FB
is the feedback voltage, V
CHG
and V
DIS
are
the parasitic voltage drop in the charge and discharge
paths, V
DROOP
is the voltage-positioning droop, and
t
OFF(MIN)
is from the
Electrical Characteristics
table. The
absolute minimum input voltage is calculated with h = 1.
If the calculated V
IN(MIN)
is greater than the required min-
imum input voltage, then reduce the operating frequency
or add output capacitance to obtain an acceptable V
SAG
.
If operation near dropout is anticipated, calculate V
SAG
to be sure of adequate transient response.
Dropout Design Example:
V
FB
= 2V
V
OUT
= 3.3V
f
SW
= 300kHz
t
OFF(MIN)
= 350ns
No droop/load line (V
DROOP
= 0)
V
CHG
and V
DIS
= 150mV (10A load)
h = 1.5:
Calculating again with h = 1 gives the absolute limit of
dropout:
Therefore, V
IN
must be greater than 4.21V, even with
very large output capacitance, and a practical input volt-
age with reasonable output capacitance would be 4.74V.
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Follow these guidelines for good PCB layout:
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
2) Connect all analog grounds to a separate solid
copper plane, which connects to the GND pin of
the Quick-PWM controller. This includes the V
CC
bypass capacitor, REF bypass capacitors, REFIN
components, and feedback compensation/dividers.
3) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCBs (2oz vs. 1oz) can enhance full-load effi-
ciency by 1% or more. Correctly routing PCB traces
is a difficult task that must be approached in terms of
fractions of centimeters, where a single mΩ of excess
trace resistance causes a measurable efficiency
penalty.
4) Keep the high-current, gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
5) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
6) Route high-speed switching nodes away from sen-
sitive analog areas (REF, REFIN, FB, ILIM).
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (low-side MOSFET source, C
IN
,
C
OUT
, and D1 anode). If possible, make all these
connections on the top layer with wide, copper-
filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is 1in
from the controller IC).
3) Group the gate-drive components (BST capacitors,
V
DD
bypass capacitor) together near the controller IC.
4) Make the DC-DC controller ground connections as
shown in the
Standard Application Circuits
. This
diagram can be viewed as having three separate
ground planes: input/output ground, where all the
high-power components go; the power ground
plane, where the PGND pin and V
DD
bypass
capacitor go, and the controller’s analog ground
plane where sensitive analog components, the
GND pin, and V
CC
bypass capacitor go. The ana-
log GND plane must meet the PGND plane only at a
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