OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NB4N316MDTG

P1-P3P4-P6P7-P9P10-P12
NB4N316M
www.onsemi.com
4
Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs V
CC
= 3.0 V to 3.6 V, V
EE
= 0 V, T
A
= −40°C to +85°C
Symbol
Characteristic Min Typ Max Unit
I
CC
Power Supply Current (Inputs and Outputs Open) 20 30 mA
R
L
= 50 W, V
TT
= 3.6 V to 2.5 V
V
OH
Output HIGH Voltage (Note 3) V
TT
− 60 V
TT
− 10 V
TT
mV
V
OL
Output LOW Voltage (Note 3) V
TT
− 1100 V
TT
− 800 V
TT
− 640 mV
|V
OD
| Differential Output Voltage Magnitude 640 780 1000 mV
R
L
= 25 W, V
TT
= 3.6 V to 2.5 V $5%
V
OH
Output HIGH Voltage (Note 3) V
TT
− 60 V
TT
− 10 V
TT
mV
V
OL
Output LOW Voltage (Note 3) V
TT
− 550 V
TT
− 400 V
TT
− 320 mV
|V
OD
| Differential Output Voltage Magnitude 320 390 500 mV
R
L
= 50 W, V
TT
= 1.8 V $5%
V
OH
Output HIGH Voltage (Note 3) V
TT
− 170 V
TT
− 10 V
TT
mV
V
OL
Output LOW Voltage (Note 3) V
TT
− 1100 V
TT
− 800 V
TT
− 640 mV
|V
OD
| Differential Output Voltage Magnitude 570 780 1000 mV
R
L
= 25 W, V
TT
= 1.8 V $5%
V
OH
Output HIGH Voltage (Note 3) V
TT
− 85 V
TT
− 10 V
TT
mV
V
OL
Output LOW Voltage (Note 3) V
TT
− 500 V
TT
− 400 V
TT
− 320 mV
|V
OD
| Differential Output Voltage Magnitude 285 390 500 mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 14 and 16)
V
th
Input Threshold Reference Voltage Range (Note 5) V
EE
V
CC
mV
V
IH
Single−ended Input HIGH Voltage V
th
+ 100 V
CC
+ 400 mV
V
IL
Single−ended Input LOW Voltage V
EE
− 400 V
th
− 100 mV
V
BB
Internally Generated Reference Voltage Supply (Loaded with −100 mA)
V
CC
− 1500 V
CC
− 1400 V
CC
− 1300 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15 and 17)
V
IHD
Differential Input HIGH Voltage V
EE
V
CC
+ 400 mV
V
ILD
Differential Input LOW Voltage V
EE
− 400 V
CC
− 100 mV
V
CMR
Input Common Mode Range (Differential Configuration) V
EE
V
CC
mV
V
ID(HYST)
Differential Input Voltage Hysteresis (V
IHD
− V
ILD
) 25 mV
|V
ID
| Differential Input Voltage Magnitude (|V
IHD
− V
ILD
|) (Note 7) 100 V
CC
− V
EE
mV
C
IN
Input Capacitance (Note 7) 1.5 pF
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. CML outputs require R
L
receiver termination resistors to V
TT
for proper operation. Outputs must be connected through R
L
to V
TT
at power
up. The output parameters vary 1:1 with V
TT
. V
TT
= 1.71 V to 3.6 V.
4. Input parameters vary 1:1 with V
CC
.
5. V
th
is applied to the complementary input when operating in single−ended mode.
6. V
CMR
(MIN) varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
.
7. Parameter guaranteed by design and evaluation but not tested in production.
NB4N316M
www.onsemi.com
5
Table 5. AC CHARACTERISTICS V
CC
= 3.0 V to 3.6 V, V
EE
= 0 V; (Note 8)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
V
OUTPP
Output Voltage Amplitude (R
L
= 50 W)
f
in
≤ 1 GHz
(See Figure 12) f
in
≤ 1.5 GHz
f
in
≤ 2.0 GHz
550
400
200
660
640
400
550
400
200
660
640
400
550
400
200
660
640
400
mV
V
OUTPP
Output Voltage Amplitude (R
L
= 25 W)
f
in
≤ 1 GHz
(See Figure 12) f
in
≤ 1.5 GHz
f
in
≤ 2.0 GHz
280
280
200
370
360
300
280
280
200
370
360
400
280
280
200
370
360
400
mV
f
DATA
Maximum Operating Data Rate 1.5 2.5 1.5 2.5 1.5 2.5 Gb/s
t
PLH
,
t
PHL
Propagation Delay to Output Differential
@ 0.25 GHz
350 550 750 350 550 750 350 550 750 ps
t
SKEW
Duty Cycle Skew (Note 9)
Device to Device Skew (Note 13)
2
20
20
100
2
20
20
100
2
20
20
100
ps
t
JITTER
RMS Random Clock Jitter R
L
= 50 W and
R
L
= 25 W (Note 11) f
in
= 750 MHz
f
in
= 1.5 GHz
f
in
= 2.0 GHz
Peak−to−Peak Data Dependent Jitter R
L
= 50 W
f
DATA
= 1.5 Gb/s
(Note 12) f
DATA
= 2.5 Gb/s
Peak−to−Peak Data Dependent Jitter R
L
= 25 W
f
DATA
= 1.5 Gb/s
(Note 12) f
DATA
= 2.5 Gb/s
1
1
1
15
20
5
10
3
3
3
55
85
35
35
1
1
1
15
20
5
10
3
3
3
55
85
35
35
1
1
1
15
20
5
10
3
3
3
55
85
35
35
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
200 200 200 mV
t
r
t
f
Output Rise/Fall Times @ 0.25 GHz Q, Q
(20% − 80%)
150 300 150 300 150 300 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
8. Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. All output loaded with an external R
L
= 50 W and R
L
= 25 W to V
TT
.
Outputs must be connected through R
L
to V
TT
at power up. Input edge rates 150 ps (20% − 80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of T
pw−
and T
pw+
@ 0.25 GHz.
10.V
INPP
(MAX) cannot exceed V
CC
− V
EE
. Input voltage swing is a single−ended measurement operating in differential mode.
11. Additive RMS jitter with 50% duty cycle clock signal.
12.Additive peak−to−peak data dependent jitter with input NRZ data signal (PRBS 2
23
−1).
13.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
Figure 3. Output Voltage Amplitude (V
OUTPP
) versus Input Clock Frequency (f
IN
) at Ambient Temperature (Typical)
0
100
200
300
400
500
600
700
800
0.75 1 1.25 1.5 1.75 2
R
L
= 50 W
R
L
= 25 W
INPUT CLOCK FREQUENCY (GHz)
OUTPUT VOLTAGE AMPLITUDE (mV)
(V
CC
− V
EE
= 3.3 V V
TT
= 3.3 V @ 255C V
in
= 100 mV)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.75 1 1.25 1.5 1.75 2
INPUT CLOCK FREQUENCY (GHz)
OUTPUT VOLTAGE AMPLITUDE (mV)
(V
CC
− V
EE
= 3.0 V V
TT
= 1.71 V @255C V
in
= 100 mV)
R
L
= 50 W
R
L
= 25 W
0.5 0.5
NB4N316M
www.onsemi.com
6
NB4N316M
0
10
20
30
40
50
60
70
80
0.5 0.75 1 1.25 1.5 1.75 2
−40°C
25°C
85°C
INPUT CLOCK FREQUENCY (GHz)
TIME (ps)
Figure 4. Data Dependent Jitter vs. Frequency
and Temperature (V
CC
− V
EE
= 3.3 V; V
TT
= 3.3 V
@ 255C; V
IN
= 100 mV; PRBS 2
23
−1; R
L
= 50 W)
0
5
10
15
20
25
30
35
0.5 0.75 1 1.25 1.5 1.75
2
25°C
−40°C
85°C
INPUT CLOCK FREQUENCY (GHz)
TIME (ps)
Figure 5. Data Dependent Jitter vs. Frequency
and Temperature (V
CC
− V
EE
= 3.3 V; V
TT
= 3.3 V
@ 255C; V
IN
= 100 mV; PRBS 2
23
−1; R
L
= 25 W)
300
350
400
450
500
550
600
−40 25 85
Figure 6. Typical Propagation Delay vs.
Temperature (V
CC
− V
EE
= 3.3 V; V
TT
= 3.3 V
@ 255C; V
in
= 100 mV; R
L
= 50 W)
TEMPERATURE (°C)
TIME (ps)
t
PD
Figure 7. Typical Propagation Delay vs. Input
Offset Voltage (V
CC
− V
EE
= 3.3 V; V
TT
= 3.3 V
@ 255C; V
in
= 100 mV R
L
= 50 W)
300
350
400
450
500
550
600
t
PD
INPUT OFFSET VOLTAGE (V)
TIME (ps)
V
EE
− 0.5 V V
CC
+ 0.5
V
V
CC
* V
EE
2
0.25 0.25
Figure 8. Supply Current vs. Temperature
0
5
10
15
20
25
30
35
−40 25 85
I
CC
TEMPERATURE (°C)
CURRENT (mA)
P1-P3P4-P6P7-P9P10-P12

NB4N316MDTG

Mfr. #:
Buy NB4N316MDTG
Manufacturer:
ON Semiconductor
Description:
Bus Receivers CML BUFF/TRANS HYST
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet