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NB4N316MDTG
P1-P3
P4-P6
P7-P9
P10-P12
NB4N316M
www
.onsemi.com
7
Figure 9. T
ypical Differential Output W
aveform at 750 Mb/s
(R
L
= 50
W
Left Plot, R
L
= 25
W
Right Plot, V
in
= 100 mV
, System DDJ = 24 ps)
Figure 10. T
ypical Differential Output W
aveform 1.5 Gb/s
(R
L
= 50
W
Left Plot, R
L
= 25
W
Right Plot, V
in
= 100 mV
, System DDJ = 25 ps)
DDJ = 5 ps
TIME (266.8 ps/div)
VOL
T
AGE (200 mV/div)
TIME (133.2 ps/div)
VOL
T
AGE (200 mV/div)
TIME (266.8 ps/div)
VOL
T
AGE (100 mV/div)
TIME (133.2 ps/div)
VOL
T
AGE (100 mV/div)
DDJ = 3 ps
DDJ = 5 ps
DDJ = 12 ps
Figure 1
1. T
ypical Differential Output W
aveform 2.5 Gb/s
(R
L
= 50
W
Left Plot, R
L
= 25
W
Right Plot, V
in
= 100 mV
, System DDJ = 24 ps)
TIME (80 ps/div)
VOL
T
AGE (200 mV/div)
TIME (80 ps/div)
VOL
T
AGE (100 mV/div)
DDJ = 20 ps
DDJ = 7 ps
NB4N316M
www
.onsemi.com
8
Figure 12. AC Reference Measurement
D
D
Q
Q
t
PHL
t
PLH
V
INPP
= V
IH
(D) − V
IL
(D)
V
OUTPP
= V
OH
(Q) − V
OL
(Q)
Figure 13. T
ypical T
ermination for Output Driver and Device Evaluation
(See Application Note AND8020/D − T
ermination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q
D
Z
o
= 50
W
Z
o
= 50
W
50
W
50
W
V
CC
Figure 14. Differential Input Driven
Single−Ended
Figure 15. Differential Inputs Driven
Differentially
Figure 16. V
th
Diagram
Figure 17. V
CMR
Diagram
D
V
CC
GND
V
IH
V
IHmin
V
IHmax
V
thmax
V
th
V
th
V
thmin
V
CMmax
V
CMmax
D
V
CMR
V
CC
GND
D
D
V
th
V
th
D
D
V
ILmax
V
IL
V
ILmin
D
V
ILCLKmax
V
IHCLKmax
V
ID
= V
IHD
− V
ILD
V
ILDtyp
V
IHDtyp
V
ILDmin
V
IHDmin
NB4N316M
www
.onsemi.com
9
D
D
V
CC
R
C
R
C
Figure 18. CML Input and Output Structure
V
EE
1.25 k
W
1.25 k
W
1.25 k
W
1.25 k
W
Input
ESD
Input
ESD
Input
ESD
Input
ESD
Internal
Current Source
V
EE
16 mA
Current Source
IN
Q
Q
IN
Input
Output
P1-P3
P4-P6
P7-P9
P10-P12
NB4N316MDTG
Mfr. #:
Buy NB4N316MDTG
Manufacturer:
ON Semiconductor
Description:
Bus Receivers CML BUFF/TRANS HYST
Lifecycle:
New from this manufacturer.
Delivery:
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