SCA61T-FA1H1G-1 Datasheet SCA61T-FA1H1G-1, SCA61T-FAHH1G-1 | P4-P6

SCA61T Series

Subject to changes 4/17

www.murata.com Doc. nr. 8261900 Rev.A3

1.3 Electrical Characteristics

Parameter

Condition

Min.

Typ

Max.

Units

Supply voltage Vdd

4.75

5.0

5.25

V

Current

consumption

Vdd = 5 V; No load 2.5 4 mA

Operating

temperature

-40 +125 °C

Analog resistive

output load

Vout to Vdd or GND 10 kOhm

Analog capacitive

output load

Vout to Vdd or GND 20 nF

Start-up delay

Reset and parity check

10

ms

1.4 SPI Interface DC Characteristics

Parameter

Conditions

Symbol

Min

Typ

Max

Unit

1.4.1.1.1 Input terminal CSB

Pull up current

V

IN

= 0 V

I

PU

13

22

35

µA

Input high voltage

V

IH

4

Vdd+0.3

V

Input low voltage

V

IL

-0.3

1

V

Hysteresis

V

HYST

0.23*Vdd

V

Input capacitance

C

IN

2

pF

1.4.1.1.2 Input terminal MOSI, SCK

Pull down current

V

IN

= 5 V

I

PD

9

17

29

µA

Input high voltage

V

IH

4

Vdd+0.3

V

Input low voltage

V

IL

-0.3

1

V

Hysteresis

V

HYST

0.23*Vdd

V

Input capacitance

C

IN

2

pF

1.4.1.1.3 Output terminal MISO

Output high voltage

I > -1mA

V

OH

Vdd-

0.5

V

Output low voltage

I < 1 mA

V

OL

0.5

V

Tristate leakage

0 < V

MISO

<

Vdd

I

LEAK

5

100

pA

1.5 SPI Interface AC Characteristics

Parameter

Condition

Min.

Typ.

Max.

Units

Output load

@500kHz

1

nF

SPI clock frequency

500

kHz

Internal A/D conversion time

150

µs

Data transfer time

@500kHz

38

µs

SCA61T Series

Subject to changes 5/17

www.murata.com Doc. nr. 8261900 Rev.A3

CSB

SCK

MOSI

MISO

T

LS1

T

CH

T

HOL

T

SET

T

VAL1

T

VAL2

T

LZ

T

LS2

T

LH

MSB in

MSB out

LSB in

LSB out

DATA out

DATA in

T

CL

1.6 SPI Interface Timing Specifications

Parameter

Conditions

Symbol

Min.

Typ.

Max.

Unit

Terminal CSB, SCK

Time from CSB (10%)

to SCK (90%)

T

LS1

120

ns

Time from SCK (10%)

to CSB (90%)

T

LS2

120

ns

Terminal SCK

SCK low time

Load

capacitance at

MISO < 2 nF

T

CL

1

µs

SCK high time

Load

capacitance at

MISO < 2 nF

T

CH

1

µs

Terminal MOSI, SCK

Time from changing MOSI

(10%, 90%) to SCK (90%).

Data setup time

T

SET

30

ns

Time from SCK (90%) to

changing MOSI (10%,90%).

Data hold time

T

HOL

30

ns

Terminal MISO, CSB

Time from CSB (10%) to stable

MISO (10%, 90%).

Load

capacitance at

MISO < 15 pF

T

VAL1

10

100

ns

Time from CSB (90%) to high

impedance state of

MISO.

Load

capacitance at

MISO < 15 pF

T

LZ

10

100

ns

Terminal MISO, SCK

Time from SCK (10%) to stable

MISO (10%, 90%).

Load

capacitance at

MISO < 15 pF

T

VAL2

100

ns

Terminal CSB

Time between SPI cycles, CSB at high

level (90%)

T

LH

15

µs

When using SPI commands RDAX, RDAY,

RWTR: Time between SPI cycles, CSB at

high level (90%)

TLH

150

µs

Figure 2. Timing diagram for SPI communication

SCA61T Series

Subject to changes 6/17

www.murata.com Doc. nr. 8261900 Rev.A3

Temperature dependency of SCA61T offset

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-40 -20 0 20 40 60 80 100 120

Temp [°C]

Offset error [degrees]

average

+3 sigma

-3 sigma

specification

limit

specification

limit

1.7 Electrical Connection

If the SPI interface is not used SCK (pin1), MISO (pin2), MOSI (pin3) and CSB (pin5) must be left

floating. Self-test can be activated applying logic “1” (positive supply voltage level) to ST pin (pin 6).

If ST feature is not used pin 6 must be left floating or connected to GND. Inclination signal is

provided from pin OUT.

Figure 3. SCA61T electrical connection

No.

Node

I/O

Description

1

SCK

Input

Serial clock

2

MISO

Output

Master in slave out; data output

3

MOSI

Input

Master out slave in; data input

4

GND

Supply

Ground

5

CSB

Input

Chip select (active low)

6

ST

Input

Self test input

7

Out

Output

8

VDD

Supply

Positive supply voltage (+5V DC)

1.8 Typical Performance Characteristics

Typical offset and sensitivity temperature dependencies of SCA61T are presented in following

diagrams. These results represent the typical performance of SCA61T components. The mean

value and 3 sigma limits (mean ± 3× standard deviation) and specification limits are presented in

following diagrams. The 3 sigma limits represents 99.73% of the SCA61T population.

Figure 4. Typical temperature dependency of the SCA61T offset

1 SCK

2 MISO

3 MOSI

4 GND

8 VDD

7 OUT

6 ST

5 CSB

SCA61T-FA1H1G-1

SCA61T-FA1H1G-1

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