MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
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face for programming of instruction code and calibra-
tion coefficients. The MAX1464 serial interface can
operate in 4-wire SPI-compatible mode or in a 3-wire
mode (default on power-up). In 3-wire mode, the DI and
DO lines can be connected together, forming a bidirec-
tional data line. The serial interface lines consist of
chip-select (CS), serial clock (SCLK), data in (DI), and
data out (DO).
The MAX1464 serial interface is selected by asserting
CS low. The serial input clock, SCLK, is gated internally
to begin sequencing the DI input data and outputting
the output data onto DO. When CS rises, the data that
was clocked into DI is loaded into an internal register
set (IRS[7:0]). The MAX1464 chip-select line CS cannot
be connected low continuously for normal operation.
The serial interface can be used both during sensor
calibration, as well as during normal operation. Each
byte of data written into the MAX1464 serial port con-
tains a 4-bit addresses nibble (IRSA [3:0]) and a 4-bit
data nibble (IRSD [3:0]). The IRS register holds both
the IRSD and IRSA nibbles as follows:
IRS [7:0] = IRSD [3:0], IRSA [3:0]
Four bytes of IRS information must be written into the
serial interface to transfer 16 bits of data through IRSD
into a MAX1464 internal register. All serial data written
into the MAX1464 is transferred through the IRS register.
The DI is read in with the LSB of the IRSA nibble first
and the MSB of the IRSD nibble last. Figure 8 shows
serial interface data input.
The IRSA bits are decoded to determine which register
the IRSD bits should be latched into. The IRSA bits
can address the DHR, the PFAR, the CR, and the IMR.
All serial data read from the serial interface is sourced
from the 16-bit DHR. Any data to be read by the serial
interface must first be placed into the internal DHR register
before being accessible for reading by the serial interface.
The entire 16-bit content of the DHR register is read out
through the DO pin by applying 16 successive clock
pulses to SCLK while CS remains low. DHR is clocked
out MSB bit first. Figure 9 shows the 4-wire mode data
read from the DHR register
In 4-wire mode, data is transferred into DI during the
clocking of data out of DO. Therefore, the last 8 bits
clocked into the DI pin during this data transfer are
latched into the IRS register and decoded when CS
returns high.
When the MAX1464 serial interface is configured in 3-
wire mode, the 16-bit DHR data is read out immediately
following the command for 3-wire mode enable. Figure
10 shows the 3-wire enable command (IRS[7:0] = 19h)
clocked into DI with a subsequent 16-bit read of DHR
on DO. DO remains in high impedance (tri-state) until
the 3-wire enable command is received. Then DO goes
into low-impedance drive mode during the next low
cycle of CS. As SCLK is clocked 16 times, the data in
DHR is clocked out at DO. The 3-wire enable command
is the command that sets the MAX1464 ready for output
on DO on the next low cycle of CS. Following the DHR
output on the low cycle of CS, the DO line returns to
high-impedance state until the next 3-wire enable com-
mand is received. The MAX1464 can receive an indefi-
nite number of inputs to DI without the need for a 3-wire
enable command to be received.
When the IRSD[3:0] nibble is written to the command
register (CR), i.e., when IRSA[3:0] = 1000, the nibble is
decoded and a command operation is initiated. The
command register decoding is shown in Table 39.
When the IRSD[3:0] nibble is written to the IMR, i.e.,
when IRSA[3:0] = 1000, the nibble is decoded and a
command operation is initiated. The IMR decoding is
shown in Table 40.
Note that after power is applied and the POR function
completes, the serial interface default is the 3-wire mode
for receiving data on DI only. The DO line is a high-
impedance output until the MAX1464 receives either the
4-wire or 3-wire mode command in the IMR. In the case
of a 3-wire mode command, DO switches from a high-
impedance state to a driving state only for the next cycle
of CS, returning to high impedance afterwards.
All commands, with the exception of programming or
erasing the FLASH memory, are completed within eight
internal master clock cycles of CS returning from low to
high. This is 4µs for a 4MHz oscillator frequency or
external clock input (1 internal master clock = 2 exter-
nal/internal oscillator periods). FLASH memory pro-
gramming and erasing require additional time of 80µs
and 4.2ms, respectively.
