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MAX1464AAI+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
______________________________________________________________________________________ 31
SE[3:0]
PGA
RANGE (V/V)
ADC
+INPUT
ADC
-INPUT
DESCRIPTION
0001 0.99 VBG V
SS
Bandgap voltage.
0010 0.99 to 244 OUTnSM V
SS
Output of small op-amp n.
0011 0.99 to 244 OUTnLG V
SS
Output of large op-amp n.
0100 0.7* V
DD
** V
SS
Power-supply voltage.
0101 0.7* V
SS
V
SS
Power-supply ground.
0110 0.7*
DACn_OUT using
OUTnSM
V
SS
DACn output through small op-amp n configured
as unity-gain buffer.
0111 0.7*
DACn_OUT using
OUTnLG
V
SS
DACn output through large op-amp n configured
as unity-gain buffer.
1000 0.99 to 244 INPn V
SS
Single-ended input on INPn.
1001 0.99 to 244 INMn V
SS
Single-ended input on INMn.
Table 7. Single-Ended (SE[3:0])
*The PGA operates at a fixed reduced gain of 0.7V/V to enable conversion of input signals at and near V
DD
and V
SS
. This gain set-
ting is not selectable.
**When measuring V
DD
, use the external reference or the 4 x V
BG
setting.
BIT NAME DESCRIPTION
15–11
PGA1[4:0]
Programmable-gain amplifier setting to use during conversion of channel 1. PGA1[4] = MSB.
10–8
CLK1[2:0]
ADC clock setting to use during conversion of channel 1. CLK1[2] = MSB.
7 — Unused.
6–4
RES1[2:0]
ADC resolution setting to use during conversion of channel 1. RES1[2] = MSB.
3 CO1[3] Coarse-offset sign bit.
2–0 CO1[2:0] Coarse-offset DAC setting to use during conversion of channel 1. CO1[2] = MSB.
Table 8. ADC_Config_1A (Address = 02h)
BIT NAME DESCRIPTION
15–7 — Unused.
6–4
BIAS1[2:0]
ADC bias setting to use during conversion of channel 1. BIAS1[2] = MSB.
3–2 — Unused.
1–0
REF1[1:0]
Reference select for conversion on channel 1. REF1[1] = MSB.
Table 9. ADC_Config_1B (Address = 03h)
BIT NAME DESCRIPTION
15–11
PGA2[4:0]
Programmable-gain amplifier to use during conversion of channel 2. PGA[4] = MSB.
10–8 CLK2[2:0] ADC clock setting to use during conversion of channel 2. CLK2[2] = MSB.
7 — Unused.
6 RES2[2:0] ADC resolution setting to use during conversion of channel 2. RES2[2] = MSB.
3 CO2[3] Coarse-offset DAC sign bit.
2–0 CO2[2:0] Coarse-offset DAC setting to use during conversion of channel 2. CO2[2] = MSB.
Table 10. ADC_Config_2A (Address = 05h)
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
32 ______________________________________________________________________________________
BIT NAME DESCRIPTION
15–7 — Unused.
6–4
BIAS2[2:0]
ADC bias setting to use during conversion of channel 2. BIAS2[2] = MSB.
3–2 — Unused.
1–0 REF2[1:0] Reference select for conversion on channel 2. REF2[2] = MSB.
Table 11. ADC_Config_2B (Address = 06h)
BITS NAME DESCRIPTION
15–11 PGAT[4:0] Programmable gain to use during conversion of temperature sensor. PGAT[4] = MSB.
10–8 CLKT[2:0] ADC clock setting to use during conversion of the temperature sensor. CLKT[2] = MSB.
7 — Unused.
6–4 REST[2:0] ADC resolution setting to use during conversion of the temperature sensor. REST[2] = MSB.
3 COT[3] Coarse-offset DAC sign bit.
2–0 COT[2:0] Coarse-offset DAC setting to use during conversion of the temperature sensor. COT[2] = MSB.
Table 12. ADC_Config_TA (Address = 08h)
BITS NAME DESCRIPTION
15–7 — Unused.
6–4
BIAST[2:0]
ADC bias setting to use during conversion of the temperature sensor. BIAST[2] = MSB.
3–0 — Unused.
Table 13. ADC_Config_TB (Address = 09h)
PGAn[4:0] GAIN (V/V)
00000 0.99
00001 7.7
00010 15.5
00011 23
00100 31
00101 39
00110 46
00111 54
01000 62
01010 77
01100 92
01110 107
10000 123
10100 153
11000 183
11100 214
11110 244
Table 14. Programmable-Gain Amplifier
(PGAn[4:0], Where n = 1, 2, or T)
CLKn[2:0] DIVISOR n f
ADC
(Hz)
000 4 1M
001 8 500k
010 16 250k
011 32 125k
100 64 62.5 k
101 128 31.25k
110 256 15.625k
111 512 7.8125k
Table 15. ADC Clock (CLKn[2:0],
Where n = 1, 2, or T; f
CLK
= 4MHz)
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
______________________________________________________________________________________ 33
RESn[2:0]
RESOLUTION (BITS)
NO. OF f
ADC
CLOCKS PER
CONVERSION
000 9 256
001 10 320
010 12 512
011 13 640
100 14 800
101 15 1280
110 16 2048
Table 16. ADC Resolution (RESn[2:0],
Where n = 1, 2, or T)
COARSE OFFSET ADDED AS % OF ADC REFERENCE*
ADC REFERENCE EQUAL TO V
DD
or 2 x V
REF
ADC REFERENCE EQUAL TO 4 x V
BG
PGAn = 1 TO 59 PGAn = 71 TO 114 PGAn = 137 TO 220 PGAn = 1 TO 59 PGAn = 71 TO 114 PGAn = 137 TO 220
COn
[3:0]
00000 TO 01000 01010 TO 10000
10100 TO 11110
00000 TO 01000 01010 TO 10000 10100 TO 11110
0111
+147 +291 +578 +137 +270 +539
0110
+124 +245 +487 +116 +229 +456
0101
+104 +206 +409 +97 +192 +383
0100
+82 +162 +322 +76 +151 +300
0011
+64 +126 +251 +59 +116 +231
0010
+41 +81 +160 +38 +75 +148
0001
+21 +41 +83 +19 +38 +76
0000
-1 -2.4 -4 -1.7 -3.3 -7
1000
-10 -19 -38 -4.6 -9 -19
1001
-30 -61 -120 -26 -51 -101
1010
-50 -100 -199 -44 -87 -174
1011
-73 -145 -287 -65 -129 -257
1100
-91 -181 -360 -82 -163 -326
1101
-113 -225 -447 -104 -205 -409
1110
-133 -264 -526 -122 -242 -482
1111
-156 -309 -614 -143 -283 -565
Table 18. Coarse-Offset DAC (3 Bits Plus Sign, Where n = 1, 2, or T)
CONVERSION TIME (ms)
RESOLUTION
(BITS)
CLKn[2:0] =
000
CLKn[2:0] =
100
CLKn[2:0] =
111
9 0.256 4.096 32.768
10 0.320 5.120 40.960
12 0.512 8.192 65.536
13 0.640 10.240 81.920
14 0.800 12.800 102.400
15 1.280 20.480 163.840
16 2.048 32.768 262.140
Table 17. ADC Conversion Time
(RESn[2:0] and CLKn[2:0], Where
n = 1, 2, or T)
*Measured at the ADC input.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47

MAX1464AAI+T

Mfr. #:
Buy MAX1464AAI+T
Manufacturer:
Maxim Integrated
Description:
16-bit Microcontrollers - MCU Low-Pwr/Nse MultiCh Sensor Signal Prcssr
Lifecycle:
New from this manufacturer.
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