OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

74AUP2G80GF,115

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
74AUP2G80 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 21 January 2013 12 of 24
NXP Semiconductors
74AUP2G80
Low-power dual D-type flip-flop; positive-edge trigger
12. Waveforms
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 8. The clock input (nCP) to output (nQ) propagation delays
001aaf311
nCP input
nQ output
t
PLH
t
PHL
V
M
V
M
V
OH
V
I
GND
nD input
V
I
GND
V
OL
V
M
V
M
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 9. The clock input (nCP) to output (nQ) propagation delays, clock pulse width, nD to nCP setup and hold
times and the nCP maximum frequency
001aaf312
t
h
t
su(L)
t
h
t
PLH
t
W
t
PHL
t
su(H)
1/f
max
V
M
V
M
V
M
V
I
GND
V
I
GND
nCP input
nD input
V
OH
V
OL
nQ output
Table 9. Measurement points
Supply voltage Output Input
V
CC
V
M
V
M
V
I
t
r
= t
f
0.8 V to 3.6 V 0.5 V
CC
0.5 V
CC
V
CC
3.0 ns
74AUP2G80 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 21 January 2013 13 of 24
NXP Semiconductors
74AUP2G80
Low-power dual D-type flip-flop; positive-edge trigger
[1] For measuring enable and disable times R
L
= 5 k
For measuring propagation delays, setup and hold times and pulse width R
L
= 1 M.
Test data is given in Table 10
.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to the output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times
001aac521
DUT
R
T
V
I
V
O
V
EXT
V
CC
R
L
5 kΩ
C
L
G
Table 10. Test data
Supply voltage Load V
EXT
V
CC
C
L
R
L
[1]
t
PLH
, t
PHL
t
PZH
, t
PHZ
t
PZL
, t
PLZ
0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M open GND 2 V
CC
74AUP2G80 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 21 January 2013 14 of 24
NXP Semiconductors
74AUP2G80
Low-power dual D-type flip-flop; positive-edge trigger
13. Package outline
Fig 11. Package outline SOT765-1 (VSSOP8)
UNIT
A
1
A
max.
A
2
A
3
b
p
LH
E
L
p
wyv
ceD
(1)
E
(2)
Z
(1)
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.1
8°
0°
0.13 0.10.20.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1 MO-187
02-06-07
w M
b
p
D
Z
e
0.12
14
8
5
θ
A
2
A
1
Q
L
p
(A
3
)
detail X
A
L
H
E
E
c
v M
A
X
A
y
2.5 5 mm0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
1
pin 1 index
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

74AUP2G80GF,115

Mfr. #:
Buy 74AUP2G80GF,115
Manufacturer:
Nexperia
Description:
Flip Flops Low-Power dual D-type flip-flop
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet