TC58NVG2S0HTAI0
2013-07-05C
1
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
4 GBIT (512M × 8 BIT) CMOS NAND E
2
PROM
DESCRIPTION
The TC58NVG2S0HTAI0 is a single 3.3V 4 Gbit (4,563,402,752 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E
2
PROM) organized as (4096 + 256) bytes × 64 pages × 2048blocks.
The device has two 4352-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 4352-byte increments. The Erase operation is implemented in a single block
unit (256 Kbytes + 16 Kbytes: 4352 bytes × 64 pages).
The TC58NVG2S0HTAI0 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
x8
Memory cell array 4352 × 128K × 8
Register 4352 × 8
Page size 4352 bytes
Block size (256K + 16K) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
• Mode control
Serial input/output
Command control
• Number of valid blocks
Min 2008 blocks
Max 2048 blocks
• Power supply
V
CC
= 2.7V to 3.6V
• Access time
Cell array to register 25 µs max
Serial Read Cycle 25 ns min (CL=50pF)
• Program/Erase time
Auto Page Program 300 µs/page typ.
Auto Block Erase 2.5 ms/block typ.
• Operating current
Read (25 ns cycle) 30 mA max.
Program (avg.) 30 mA max
Erase (avg.) 30 mA max
Standby 50 µA max
• Package
TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
• 8 bit ECC for each 512Byte is required.